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| 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2002-2005, zarlink semiconductor inc. all rights reserved. features ? 12,288-channel x 12,288-channel non-blocking unidirectional switching.the backplane and local inputs and outputs can be combined to form a non-blocking switching matrix with 48 stream inputs and 48 stream outputs ? 8,192-channel x 4,096-channel blocking backplane to local stream switch ? 4,096-channel x 8,192-channel non-blocking local to backplane stream switch ? 8,192-channel x 8,192-channel non-blocking backplane input to backplane output switch ? 4,096-channel x 4,096-channel non-blocking local input to local output stream switch ? rate conversion on all data paths, backplane to local, local to backplane, backplane to backplane and local to local streams ? backplane port accepts 32 st-bus streams with data rates of 2.048 mb/s, 4.096 mb/s, 8.192 mb/s or 16.384 mb/s in any combination, or a fixed allocation of 16 streams at 32.768 mb/s ? local port accepts 16 st-bus streams with data rates of 2.048 mb/s, 4.096 mb/s, 8.192 mb/s or 16.384 mb/s, in any combination ? per-stream channel and bit delay for local input streams ? per-stream channel and bit delay for backplane input streams ? per-stream advancement for local output streams ? per-stream advancement for backplane output streams MT90870 flexible 12 k digital switch (f12kdx) data sheet ordering information MT90870ag 272 ball pbga trays MT90870ag2 272 ball pbga* trays *pb free tin/silver/copper -40 to +85 o c *note : the package thickness is different than the MT90870ag (see drawing at the end of the data sheet). november 2005 figure 1 - MT90870 functional block diagram backplane data memories (8,192 channels) ds cs r/w a14-a0 dta d15-d0 test port microprocessor interface and internal registers v ss (gnd) v dd_core tdi tdo tck trst tms lsto0-15 (4,096 locations) reset local interface connection memory bsti0-31 backplane timing unit fp8i pll lsti0-15 interface backplane bsto0-31 local c8i v dd_io lcst0-1 ode bcst0-3 c8o c16o fp8o fp16o v dd_pll local timing unit (8,192 locations) connection memory backplane interface local local data memories (4,096 channels) bors lors
MT90870 data sheet 2 zarlink semiconductor inc. ? constant throughput delay for frame integrity ? per-channel high impedance output control for local and backplane streams ? per-channel driven-high output control for local and backplane streams ? high impedance-control outputs for external drivers on backplane and local port ? per-channel message mode for local and backplane output streams ? connection memory block programming for fast device initialization ? automatic selection between st-bus and gci-bus operation ? non-multiplexed motorola microprocessor interface ? ber testing for local and backplane ports ? conforms to the mandatory requirements of the ieee-1149.1 (jtag) standard ? memory built-in-self-test (bist), controlled via microprocessor registers ? 1.8 v core supply voltage ? 3.3 v i/o supply voltage ? 5 v tolerant inputs, outputs and i/os ? per streams subrate switching at 4 bit, 2 bit and 1 bit depending on stream data rate applications ? central office switches (class 5) ? mediation switches ? class-independent switches ? access concentrators ? scalable tdm-based architectures ? digital loop carriers device overview the MT90870 has two data ports, the backplane and th e local port. the backplane port has two modes of operation, either 32 input and 32 out put streams operated at 2.048 mb/s, 4.096 mb/s, 8.192 mb/s or 16.384 mb/s, in any combination, or 16 input and 16 output streams operated at 32.768 mb/s. the local port has 16 input and 16 output streams operated at 2.048 m b/s, 4.096 mb/s, 8.192 mb/s or 16.384 mb/s, in any combination. the MT90870 contains two data memory blocks (backplane and local) to provide the following switching path configurations: ? backplane-to-local, supporting 8 k x 4 k data switching, ? local-to-backplane, supporting 4 k x 8 k data switching, ? backplane-to-backplane, supporting 8 k x 8 k data switching. ? local-to-local, supporting 4 k x 4 k data switching. the device contains two connection memory blocks, one for the backplane output and one for the local output. data to be output on the seri al streams may come from ei ther of the data memories (connection mode) or directly from the connection memory contents (message mode). MT90870 data sheet 3 zarlink semiconductor inc. in connection mode the contents of the connection me mory defines, for each output stream and channel, the source stream and channel (stored in data memory) to be switched. in message mode, microprocessor data can be writt en to the connection memory for broadcast on the output streams on a per channel basis. this feature is useful for tran sferring control and status information to external circuits or other st-bus devices. the device uses a master frame pulse (fp8i ) and master clock (c8i ) to define the frame boundary and timing for both the backplane port and the local port. the device will automatically detect whether an st-bus or a gci-bus style frame pulse is being used. there is a two frame delay from the time reset is de-asserted to the establishment of full switch functionality. during this peri od the frame format is determined before switching begins. the device provides fp8o , fp16o , c8o and c16o outputs to support external devices connected to the local port. subrate switching is accomplished by oversampling (i.e., 1 bit switching can be accomplished by sampling a 2 mb/s stream at 16 mbps). refer to msan-175. a non-multiplexed motorola microprocessor port allows programming of the various device operation modes and switching configurations. the micropro cessor port provides access for r egister read/write, connection memory read/write and data memory read-only operations. the port has a 15-bit addr ess bus, 16-bit data bus and 4 control signals. the microprocessor may monitor channel data in the backplane and local data memories. the mandatory requirements of the ieee-1149.1 (jtag) st andard are fully supported via a dedicated test port. the MT90870 is manufactured in a 27 mm x 27 mm body, 1.27 mm ball-pitch, 272-pbga to jedec standard ms-034 bal-2 iss. a. MT90870 data sheet table of contents 4 zarlink semiconductor inc. 1.0 bidirectional and unidirectional applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.1 flexible configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1 switching configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1.1 backplane-to-local path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.2 local-to-backplane path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.3 backplane-to-backplane path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.4 local-to-local path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.5 uni-directional switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 port data rate modes and selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.1 local port rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.1.1 local input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.1.2 local output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.2 backplane port rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.2.1 backplane input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.2.2 backplane output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 backplane frame pulse input and master input clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4 backplane frame pulse input and local frame pulse output alignment. . . . . . . . . . . . . . . . . . . . . . . . . 24 3.0 input and output offset programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 input channel delay programming (backp lane and local input streams) . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 input bit delay programming (backplane and local input streams) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3 output advancement programming (backplane and local output streams) . . . . . . . . . . . . . . . . . . . . . . 27 3.3.1 local output advancement programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 3.3.2 backplane output advancement programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.0 port high impedance control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 local port high impedance control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.1 lors set low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 backplane high impedance control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.1 bors set low, non-32 mb/s mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.2 bors set low, 32 mb/s mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.3 bors set high. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.0 data delay through the switching paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.0 connection memory description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1 local connection memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2 backplane connection memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3 connection memory block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3.1 memory block programming pr ocedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.0 microprocessor port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.0 device power-up, initialization and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.1 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.2 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.0 bit error rate test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.0 memory built-in-self-test (bist) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.0 jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.1 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.2 tap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.1 test instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.2 test data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.2.1 the boundary-scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.2.2 the bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MT90870 data sheet table of contents 5 zarlink semiconductor inc. 11.2.2.3 the device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.3 boundary scan description language (bsdl) file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.0 memory address mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1 backplane data memory bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.2 local data memory bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.3 local connection memory bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.4 backplane connection memory bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.5 internal register mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.0 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.1 control register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.2 block programming register (bpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.3 bit error rate test control register (bercr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13.4 local input channel delay registers (lcdr0 to lcdr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 13.4.1 local channel delay bits 7-0 (lcd7 - lcd0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 13.5 local input bit delay registers (lidr0 to lidr15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 13.5.1 local input delay bits 4-0 (lid4 - lid0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 13.6 backplane input channel delay registers (bcdr0 to bcdr31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13.6.1 backplane channel delay bits 8-0 (bcdn8 - bcdn0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13.7 backplane input bit delay registers (b idr0 to bidr31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.7.1 backplane input delay bits 4-0 (bid4 - bid0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.8 local output advancement registers (loar0 to loar15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.8.1 local output advancement bits 1-0 (loa1-loa0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13.9 backplane output advancement registers (boar0 - 31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 13.9.1 backplane output advancement bits 1-0 (boa1-boa0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13.10 local bit error rate (ber) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13.10.1 local ber start send register (lbssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13.10.2 local transmit ber length register (ltxblr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13.10.3 local receive ber length register (lrxblr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13.10.4 local ber start receive register (lbsrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 13.10.5 local ber count register (lbcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13.11 backplane bit error rate (ber) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13.11.1 backplane ber start send register (bbssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13.11.2 backplane transmit ber length register (btxblr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13.11.3 backplane receive ber length register (brxblr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.11.4 backplane ber start receive register (bbsrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.11.5 backplane ber count register (bbcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 13.12 local bit rate registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.12.1 local input bit rate registers (lib rr0-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.12.2 local output bit rate resisters (lobrr0-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.13 backplane bit rate registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.13.1 backplane input bit rate registers (bibrr0-31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 13.13.2 backplane output bit rate registers (bobrr0-31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.14 memory bist register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13.15 revision control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 MT90870 data sheet list of figures 6 zarlink semiconductor inc. figure 1 - MT90870 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - MT90870 pbga connections (272 pbga) pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3 - 8,192 x 4,096 channels (16 mb/s), bidirectional switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4 - 12,288 x 12,288 channels (16 mb/s), unidirectional switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5 - 6 k x 6 k non-blocking configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6 - local port timing diagram for 2,4,8 and 16 mb/s stream rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7 - backplane port timing diagram for 2, 4, 8, 16 and 32 mb/s stream rates . . . . . . . . . . . . . . . . . . . . . . 23 figure 8 - backplane and local frame pulse alignment fo r data rates of 2 mb/s, 4 mb/s, 8 mb/s and 16 mb/s. 24 figure 9 - backplane and local input channel delay timing diagram (8 mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10 - backplane and local input bit delay timing diagram for data rate of 16 mb/s. . . . . . . . . . . . . . . . . 26 figure 11 - backplane and local input bit delay timing diagram for data rate of 8 mb/s. . . . . . . . . . . . . . . . . . 27 figure 12 - backplane and local output advancement timing diagram for data rate of 16 mb/s. . . . . . . . . . . . 28 figure 13 - local port external high impedance control bit timing (st-bus mode) . . . . . . . . . . . . . . . . . . . . . . 32 figure 14 - backplane port external high impedance control bit timing (non-32 mb/s mode) . . . . . . . . . . . . . . 36 figure 15 - backplane port external high impedance control timing (32 mb/s mode) . . . . . . . . . . . . . . . . . . . . 40 figure 16 - constant switch delay: examples of different str eam rates and routing . . . . . . . . . . . . . . . . . . . . . 41 figure 17 - examples of ber transmission channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 18 - frame boundary conditions, st- bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 19 - frame boundary conditions, gci - bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 20 - backplane and local clock timing diagram for st-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 21 - backplane and local clock timing for gci-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 22 - st-bus backplane data timing diagram (8 mb/s, 4 mb/s, 2 mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 23 - st-bus backplane data timing diagram (32 mb/s, 16 mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 figure 24 - gci bus backplane data timing diagram (8 mb/s, 4 mb/s, 2 mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 25 - gci bus backplane data timing diagram (32 mb/s, 16 mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 26 - st-bus local timing diagram (16 mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 27 - st-bus local data timing diagram (8 mb/s, 4 mb/s, 2 mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 28 - serial output and external control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 29 - output driver enable (ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 30 - motorola non-multiplexed bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 MT90870 data sheet list of tables 7 zarlink semiconductor inc. table 1 - per-stream data-rate selection: backplane and local, non-32 mb/s mode and 32 mb/s mode. . . . . . 21 table 2 - lcsto allocation of channel control bits to the output streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 3 - bcsto allocation of channel control bits to the output streams (non-32 mb/s mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 4 - bcsto allocation of channel control bits to the output streams (32 mb/s mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5 - local and backplane connection memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 6 - local connection memory in block programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 7 - backplane connection memory in block programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 8 - address map for data and connection memory locations (a14=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 table 9 - backplane data memory (bdm) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 10 - local data memory (ldm) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 11 - lcm bits for local-to-local and backplane (non-32 mb/s mode)-to-local switching . . . . . . . . . . . . . 49 table 12 - lcm bits for backplane(32 mb/s mode)-to-local switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 13 - bcm bits for local-to-backplane and backplane-to-backplane switching (non-32 mb/s mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 14 - bcm bits for backplane-to-backplane switching (32 mb/s mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 15 - address map for register (a14 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 16 - control register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 18 - bit error rate test control register (bercr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 17 - block programming register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 19 - local channel delay register (lcdrn) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 20 - local input channel delay programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 21 - local channel delay register (lidrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 22 - local input bit delay programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 23 - backplane channel delay register (bcdrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 24 - backplane input channel delay (bcd) programming table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 25 - backplane input bit delay register (bidrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 26 - backplane input bit delay programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 27 - local output advancement register (loarn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 28 - local output advancement (loar) programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 29 - backplane output advancement regi ster (boar) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 30 - backplane output advancement (boar) programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 table 31 - local ber start send register (lbssr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 32 - local transmit ber length register (ltxblr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 33 - local receive ber length register (lrxblr) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 34 - local ber start receive register (lbsrr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 35 - local ber count register (lbcr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 36 - backplane ber start send register (bbssr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 37 - backplane transmit ber length (btxblr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 38 - backplane receive ber length (brxblr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 39 - backplane ber start receive register (bbsrr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 40 - backplane ber count register (bb cr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 41 - local input bit rate register (librrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 42 - local input bit rate (libr) programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 43 - local output bit rate register (lobrrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 44 - output bit rate (lobr) programming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 45 - backplane input bit rate register (bibrrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 46 - backplane input bit rate (bibr) programming table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 MT90870 data sheet list of tables 8 zarlink semiconductor inc. table 47 - backplane output bit rate register (bobrrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 49 - memory bist register (mbistr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 50 - revision control register (rcr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 MT90870 data sheet 9 zarlink semiconductor inc. changes summary the following table captures the changes from the december 2002 issue. page item change 14 pin description , c8i the internal frame boundary alignment description is changed from the clock rising or falling edge to rising edge only. also added description to specify setting the c8ipol bit in the control register to one for clock rising e dge alignment operation. 21 figure 6, local port timing diagram for 2,4,8 and 16 mb/s stream rates changed c8i frame boundary active edge from falling to rising edge. 23 figure 7, backplane port timing diagram for 2, 4, 8, 16 and 32 mb/s stream rates changed c8i frame boundary active edge from falling to rising edge. 23 section 2.3. backplane frame pulse input and master input clock timing removed the falling clock edge frame boundary alignment option. 24 figure 8, backplane and local frame pulse alignment for data rates of 2 mb/s, 4 mb/s, 8 mb/s and 16 mb/s changed c8i frame boundary active edge from falling to rising edge. 25 figure 9, backplane and local input channel delay timing diagram (8 mb/s) changed fpo and c8o to fpi and c8i respectively and showing rising c8i frame boundary active edge. 26 figure 10, backplane and local input bit delay timing diagram for data rate of 16 mb/s changed fpo and c8o to fpi and c8i respectively and showing rising c8i frame boundary active edge. 27 figure 11, backplane and local input bit delay timing diagram for data rate of 8mb/s changed fpo and c8o to fpi and c8i respectively. 52 section 13.1. control register (cr) bit 6, c8ipol changed description to specify bit 6, c8ipol must be set high for rising clock edge frame boundary alignment operation. 53 figure 18, frame boundary conditions, st- bus operation removed waveforms showing c8i falling edge frame boundary option. 54 figure 19, frame boundary conditions, gci - bus operation removed waveforms showing c8i falling edge frame boundary option. 73 backplane and local clock timing : item 2, backplane frame pulse setup time before c8i clock falling edge item 3, backplane frame pulse hold time from c8i clock falling edge item 2, backplane frame pulse setup time before c8i clock falling edge changed to backplane frame pulse setup time before c8i clock rising edge. item 3, backplane frame pulse hold time from c8i clock falling edge changed to backplane frame pulse hold time from c8i clock rising edge. MT90870 data sheet 10 zarlink semiconductor inc. 75 figure 20, backplane and local clock timing diagram for st-bus changed c8i frame boundary active edge from falling to rising edge. 78 figure 22, st-bus backplane data timing diagram (8 mb/s, 4 mb/s, 2 mb/s) changed c8i frame boundary active edge from falling to rising edge. 79 figure 23, st-bus backplane data timing diagram (32 mb/s, 16 mb/s) changed c8i frame boundary active edge from falling to rising edge. 82 figure 26, st-bus local timing diagram (16 mb/s) changed c8i frame boundary active edge from falling to rising edge. 82 figure 27, st-bus local data timing diagram (8 mb/s, 4 mb/s, 2 mb/s) changed fpo and c8o to fpi and c8i respectively and shows rising c8i frame boundary active edge. page item change MT90870 data sheet 11 zarlink semiconductor inc. figure 2 - MT90870 pbga connections (272 pbga) pin diagram (as viewed through top of package) 11 12 13 14 15 16 17 18 tck trst bcsto0 lsto0 ic lcsto0 lsto6 lsto3 lsto1 lcsto1 bcsto3 nc bcsto2 nc bcsto1 tdi dta vdd_core ode ds cs tdo reset r/w gnd gnd gnd vdd_pll gnd ic ic c8o ic ic ic ic ic c8i c16o ic ic ic ic vdd_core nc nc ic ic ic ic ic ic lsti0 lsti4 vdd_io gnd ic vdd_core 20 lsti12 lsti9 lsti15 ic lsto5 ic lsto8 ic ic ic ic lsto15 lsti6 ic ic ic ic vdd_core lsti2 19 lsti11 lsti8 lsti14 ic lsto4 lsto2 lsto7 ic ic ic ic lsto14 lsti5 ic ic ic ic lors lsti1 lsto13 ic ic ic lsti7 vdd_core ic vdd_core gnd lsto9 ic vdd_io gnd tms vdd_io lsto11 lsto10 b c d f g h j l m n a p r t u v w y ic ic vdd_io lsti3 lsto12 vdd_io ic gnd gnd lsti10 vdd_core gnd gnd gnd gnd gnd gnd lsti13 vdd_io fp8i fp8o fp16o vdd_core k e b c d e f g h j k l m n 1 2 3 4 5 6 78910 a p r t bsto2 bsto26 bsto1 bsto0 a8 a7 a6 bsto14 bsto16 bsto15 bsti7 bsti10 vdd_core bsti14 gnd bsti9 bsti13 bsti12 bsti16 vdd_io bsti17 bsti19 bsti20 bsti21 a13 ic a14 ic a10 a11 a4 a1 a5 ic vdd_core a2 vdd_core bsto4 bsto8 bsto5 ic bsto6 bsto7 bsto3 bsto13 ic bsto10 bsto12 bsto9 bsto11 bsto20 bsto23 bsto22 bsto19 bsto18 bsto21 bsto27 bsto29 bsto30 bsto28 bsti0 bors vdd_core bsti1 bsti2 bsti3 bsti5 bsti6 bsti15 gnd u ic ic gnd v ic ic bsti29 d13 d7 d3 d0 d9 w bsti24 bsti25 bsti30 d12 d6 d2 ic d8 y bsti27 ic bsti31 d11 d5 d1 ic vdd_core gnd gnd bsto17 bsti8 vdd_io bsto24 gnd bsto31 vdd_io bsti4 vdd_io gnd d4 vdd_io d10 gnd a0 gnd a12 a9 a3 vdd_io gnd gnd gnd gnd gnd gnd bsti11 bsti18 bsti22 bsti28 vdd_core vdd_core bsti23 d15 d14 bsti26 bsto25 a1 corner identified by metallized marking MT90870 data sheet 12 zarlink semiconductor inc. pin description name package coordinates description v dd_io d6, d11, d15, f4, f17, k4, l17, r4, r17, u6, u10, u15 power supply for periphery circuits: +3.3 v v dd_core a7, b4, b12, d14, k1, k20, n3, p18, t17, u16, v1, v5, y7, y11, y14 power supply for core logic circuits: +1.8 v v dd_pll u12 power supply for analogue pll: +1.8 v v ss (gnd) a1, d4, d8, d13, d17, h4, h17, j9, j10, j11, j12, k9, k10, k11, k12, l9, l10, l11, l12, m9, m10, m11, m12, n4, n17, u4, u8, u11, u13, u17 ground bsti0 - 15 k3, l1, l2, l3, l4, m1, m2, m3, m4, n1, n2, p1, p2, p3, p4, r1 backplane serial input streams 0 to 15 (5 v tolerant, internal pull- down). in non-32 mb/s mode, these pins accept serial tdm data streams at a data-rate of: 16.384 mb/s (with 256 channels per stream), 8.192 mb/s (with 128 channels per stream), 4.096 mb/s (with 64 channels per stream), or 2.048 mb/s (with 32 channels per stream). the data-rate is independently progr ammable for each input stream. in 32 mb/s mode, these pins accept serial tdm data streams at a fixed data-rate of 32.768 mb/s (with 512 channels per stream). bsti16 - 31 r2, r3, t1, t2, t3, t4, u1,w1, w2, w3, y1, y2, u5, v4, w4, y4 backplane serial input streams 16 to 31 (5 v tolerant, internal pull- down). in non-32 mb/s mode, these pins accept serial tdm data streams at a data-rate of: 16.384 mb/s (with 256 channels per stream), 8.192 mb/s (with 128 channels per stream), 4.096 mb/s (with 64 channels per stream), or 2.048 mb/s (with 32 channels per stream). the data-rate is independently progr ammable for each input stream. in 32 mb/s mode, these pins are unused and should be externally connected to a defined logic level. MT90870 data sheet 13 zarlink semiconductor inc. bsto0 - 15 c5, b5, a5 c4, a4, a3, b1, b2, b3, c1, c2, d1, d2, d3, e1, e2 backplane serial output streams 0 to 15 (5 v tolerant, three-state outputs). in non-32 mb/s mode, these pins output serial tdm data streams at a data-rate of: 16.384 mb/s (with 256 channels per stream), 8.192 mb/s (with 128 channels per stream), 4.096 mb/s (with 64 channels per stream), or 2.048 mb/s (with 32 channels per stream). the data-rate is independently progr ammable for each output stream. in 32 mb/s mode, these pins output se rial tdm data streams at a fixed data-rate of 32.768 mb/s (with 512 channels per stream). refer to descriptions of the bors and ode pins for control of the output high or high-impedance state. bsto16 - 31 e3, e4, f1, f2, f3, g1, g2, g3, g4, h1, h2, h3, j1, j2, j3, j4 backplane serial output streams 16 to 31 (5 v tolerant three-state outputs). in non-32 mb/s mode, these pins output serial tdm data streams at a data-rate of: 16.384 mb/s (with 256 channels per stream), 8.192 mb/s (with 128 channels per stream), 4.096 mb/s (with 64 channels per stream), or 2.048 mb/s (with 32 channels per stream). the data-rate is independently progr ammable for each output stream. these pins are unused when the 32 mb/s mode is selected. refer to descriptions of the bors and ode pins for control of the output high or high-impedance state. pin description (continued) name package coordinates description MT90870 data sheet 14 zarlink semiconductor inc. bcsto0-3 c14, a15, b15, c15 backplane output channel high impedance control (5 v tolerant three-state outputs). active high output enable which may be used to control external buffering individua lly for a set of backplane output streams on a per channel basis. in non-32 mb/s mode (stream rates 2 mb/s to 16 mb/s): bcsto0 is the output enable for bsto[0,4,8, 12,16,20,24,28], bcsto1 is the output enable for bsto[1,5,9, 13,17,21,25,29], bcsto2 is the output enable for bsto[2,6,10, 14,18,22,26,30], bcsto3 is the output enable for bsto[3,7,11 ,15,19,23,27,31]. in 32 mb/s mode (stream rate 32 mb/s): bcsto0 is the output enable for bsto[0,4,8,12], bcsto1 is the output enable for bsto[1,5,9,13], bcsto2 is the output enable for bsto[2,6,10,14], bcsto3 is the output enable for bsto[3,7,11,15]. refer to descriptions of the bors and ode pins for control of the output high or high-impedance state. fp8i u14 frame pulse input (5 v tolerant). this pin accepts the frame pulse signal. the pulse width may be active for 122 ns or 244 ns at the frame boundary and the frame pulse width bi t (fpw) of the control register must be set low (default) for a 122 ns and set high for a the 244 ns pulse condition.the device will automatically detect whether an st-bus or gci- bus style frame pulse is applied. c8i w12 master clock input (5 v tolerant). this pin accepts a 8.192 mhz clock. the internal frame boundary is aligned with the rising edge of this clock. this rising edge frame boundary alignment is controlled by the c8ipol bit in the control register as shown in table 16 on page 52. the c8ipol bit must be set to one for the rising edge frame boundary to be detected correctly. falling c8i edge frame boundary alignment is not supported and should not be used. cs b11 chip select (5 v tolerant). active low input used by the microprocessor to enable the microprocessor port access. this input is internally set low during a device reset . ds a11 data strobe (5 v tolerant). this active low input works in conjunction with cs to enable the microprocessor port read and write operations. r/w c11 read/write (5 v tolerant). this input controls the direction of the data bus lines (d0-d15) during a microprocessor access. a0 - a14 d5, c6, a6, d7, c7, b7, c8, b8, a8, d9, b9, a9, d10, c10, a10 address 0 - 14 (5 v tolerant). these pins form the 15-bit address bus to the internal memories and registers. (address a0 = lsb). pin description (continued) name package coordinates description MT90870 data sheet 15 zarlink semiconductor inc. d0 - d15 v10, y9, w9, v9, u9, y8, w8, v8, w7, v7, u7, y6, w6, v6, y5, w5 data bus 0 - 15 (5 v tolerant). these pins form the 16-bit data bus of the microprocessor port. (data d0 = lsb). dta a13 data transfer acknowledgment (5 v tolerant). this active low output indicates that a data bus transfer is complete. a pull-up resistor is required to hold a high level. (max. i ol = 10ma). tms d12 test mode select (5 v tolerant with internal pull-up). jtag signal that controls the state transitions of the tap controller. tck a14 test clock (5 v tolerant). provides the clock to the jtag test logic. tdi b13 test serial data in (5 v tolerant with internal pull-up). jtag serial test instructions and data are shifted in on this pin. tdo c13 test serial data out (5 v to lerant three-state output). jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag is not enabled. trst b14 test reset (5 v tolerant with internal pull-up) asynchronously initializes the jtag tap controller to the test-logic-re set state. to be pulsed low during power-up for jtag testing. this pin must be held low for normal functional operation of the device. reset c12 device reset (5 v tolerant with internal pull-up). this input (active low) asynchronously applies reset and synchronously releases reset to the device. in the reset state, the outputs lsto0 - 15 and bsto0 - 31 are set to a high or high impedance depe nding on the state of the lors and bors external control pins, respecti vely. it clears the device registers and internal counters. this pin must stay low for more than 2 cycles of input clock c8i for the reset to be invoked. lsti0-15 l18, l19, l20, m17, m18, m19, m20, n18, n19, n20, p17, p19, p20, r18, r19, r20, local serial input streams 0 to 15 (5 v tolerant with internal pull- down). these pins accept serial tdm data streams at a data-rate of: 16.384 mb/s (with 256 channels per stream), 8.192 mb/s (with 128 channels per stream), 4.096 mb/s (with 64 channels per stream), or 2.048 mb/s (with 32 channels per stream). the data-rate is independently progr ammable for each input stream. c16o w13 c16o output clock (thr ee-state output). a 16.384 mhz clock output. the clock falling edge or rising edge is aligned with the local frame boundary, this is controlled by the copol bit of the control register. c8o v13 c8o output clock (three-state output). a 8.192 mhz clock output. the clock falling edge or rising edge is a ligned with the local frame boundary, this is controlled by the copo l bit of the control register. pin description (continued) name package coordinates description MT90870 data sheet 16 zarlink semiconductor inc. fp16o w14 frame pulse output (three-state output). frame pulse output is active for 61 ns at the frame boundary. the fr ame pulse, running at a 8 khz rate, will be the same format (st-bus or gci-bus) as the input frame pulse (fp8i) . fp8o v14 frame pulse output (three-state output). frame pulse output is active for 122 ns at the frame boundary. the frame pulse, running at 8 khz rate, will be the same style (st-bus or gci-bus) as the input frame pulse (fp8i) . lsto0 - 15 a17, a18, a19, b18, b19, b20, c18, c19, c20, d18, d19, d20, e17, e18, e19, e20, local serial output streams 0 to 15 (5 v tolerant three-state outputs). these pins output serial tdm da ta streams at a data-rate of: 16.384 mb/s (with 256 channels per stream), 8.192 mb/s (with 128 channels per stream), 4.096 mb/s (with 64 channels per stream), or 2.048 mb/s (with 32 channels per stream). the data-rate is independently progr ammable for each output stream. refer to descriptions of the lors and ode pins for control of the output high or high-impedance state. lcsto0-1 c17, c16 local output channel high impedance control (5 v tolerant three- state outputs). active high output enable: used to control, on a per-channel basis, the external buffering of local output streams. lcsto0 is the output enable for streams: lsto[0,2,4,6,8,10,12, and 14]. lcsto1 is the output enable for streams: lsto[1,3,5,7,9,11,13, and 15]. refer to descriptions of the lors and ode pins for control of the output high or high-impedance state. ode a12 output drive enable (5 v to lerant, internal pull-up). an asynchronous input providing outp ut enable control to the bsto0- 31, lsto0-15, bcsto0-3 and lcsto0-1 outputs. when low, the bsto0-31 and lsto0- 31 outputs are driven high or high impedance (dependent on the bors and lors pin settings respectively) and the outputs bcsto0-3 and lcsto0-1 are driven low. when high, the outputs bsto0- 31, lsto0-15, bcsto0-3 and lcsto0-1 are enabled. pin description (continued) name package coordinates description MT90870 data sheet 17 zarlink semiconductor inc. bors k2 backplane output reset state (5 v tolerant, internal pull-down). when this input is low the device w ill initialize with the bsto0-31 outputs driven high, and the bcsto0-3 outputs dr iven low. following initialization, the backplane stream outputs are al ways active and a high impedance state, if required on a per-channel basis, may be implemented with external buffers controlled by outputs bcsto0-3. when this input is high, the devic e will initialize with the bsto0-31 outputs at high impedance and the bcsto0-3 outputs driven low. following initialization, the backplane stream outputs may be set active or high impedance using the ode pin, or on a per- channel basis with the be bit of the backplane connection memory. lors k19 local output reset state (5 v tolerant, internal pull-down). when this input is low, the device will initialize with the lsto0-15 outputs driven high and the lcsto0-1 outputs driven low. following initialization, the local stream outputs are always active and a high impedance state, if required on a per-channel basis, may be implemented with external buffers controlled by the lcsto0-1 outputs. when this input is high, the devic e will initialize with the lsto0-15 outputs at high impedance and the lcsto0-1 outputs driven low. following initialization, the local stre am outputs may be set active or high impedance using the ode pin, or on a per-channel basis with the le bit of the local connection memory. nc a16, b16, y12, y13 no connect. no connection to be made. ic a2, a20, b6, b10, b17, c3, c9, d16, u2, u3, v2, v3, v11, v12, v15, v16, w10, w11, w15, w16, w17, w20, y3, y10, y15, y16, t18, t19, t20, u18, u19, u20, v17, v18, v19, v20, w18, w19, y20, y17, y18, y19, f18, f19, f20, g17, g18, g19, g20, h18, h19, h20, j17, j18, j19, j20, k17, k18 internal connects these inputs must be held low. pin description (continued) name package coordinates description MT90870 data sheet 18 zarlink semiconductor inc. 1.0 bidirectional and unidirectional applications the MT90870 has a maximum capacity of 12,288 input c hannels and 12,288 output channel s. this is calculated from the maximum number of streams and channels: 48 in put streams (32 backplane, 16 local) at 16.384 mb/s and 48 output streams (32 backpl ane, 16 local) at 16.384 mb/s. one typical mode of operation is to separate the backplane and local sides, as shown in figure 3 below. figure 3 - 8,192 x 4,096 channels (16 mb/s), bidirectional switching in this system setup, the chip has a capacity of 8,192 input channels and 8,192 output channels on the backplane side as well as 4,096 input channels and 4,096 output c hannels on the local side. note that some of the output channels on one side can come from the other side , i.e., backplane input to local output switching. often a system design does not need to differentiate between backplane and local side, and merely needs maximum switching capacity. in this case, the MT90870 can be used as shown in figure 4 to give the full 12,288 x 12,288 channel capacity. figure 4 - 12,288 x 12,288 channels (1 6 mb/s), unidirectional switching in this system, the backplane and local inputs and out puts are combined and the sw itch appears as a 48 stream input by 48 stream output switch. this style of operation is similar to older switch designs, such as the mt90826. note, in either configurat ion the backplane may be operated in t he 32 mb/s mode, providing 512 channels on each of the 16 available input and output streams (bsti0-15 and bsto0-15) operat ing at a data-rate of 32.768 mb/s, in conjunction with the local streams (lsti0-15 and lsto0- 15) operated at 16.384 mb/s. this allows data-rate conversion between 32.768 mb/s and 16.384 mb/s without loss to the switching capacity. MT90870 32 streams 32 streams 16 streams 16 streams bsti0-31 bsto0-31 lsto0-15 lsti0-15 backplane local MT90870 32 streams 16 streams 32 streams 16 streams bsti0-31 lsti0-15 bsto0-31 lsto0-15 input output MT90870 data sheet 19 zarlink semiconductor inc. 1.1 flexible configuration the f12kdx can be configured as an 8 k by 4 k blocking bi-directional digital switch, a 12 k by 12 k unidirectional non-blocking digital switch, and as a non-blocki ng switch with various switching capacities. a. blocking bi-directional configurat ion (typical system configuration) ? 8,192-channel x 4,096-channel blocking swit ching from backplane to local streams ? 4,096-channel x 8,192-channel blocking swit ching from local to backplane streams ? 8,192-channel x 8,192-channel non-blocking switchin g from backplane input to backplane output streams ? 4,096-channel x 4,096-channel non-blocking switchin g from local input to local output streams b. unidirectional configuration because the input and output drivers are synchronous, the user can comb ine input backplane streams and input local streams or output ba ckplane streams and output loca l streams to increase the total number of input and output streams of the switch in a unidirectional configuration. ? 12,288-channel x 12,288-channel non-blocking sw itching from input to output streams c. non-blocking configuration the f12kdx can be configured as a non-blocking switch if it is an application requirement. for example, it can be configured as a 6 k by 6 k non-blocking switch: ? 6,144-channel x 6,144-channel non-blocking swit ching from "backplane" to "local" streams ? 6,144-channel x 6,144-channel non-blocking swit ching from "local" to "backplane" streams ? 6,144-channel x 6,144-channel non-blocking switchin g from "backplane" input to "backplane" output streams ? 6,144-channel x 6,144-channel non-blocking switchin g from local input to local output streams figure 5 - 6 k x 6 k non-blocking configuration 2.0 functional description 2.1 switching configurations the device supports five switching c onfigurations. (1) backplane-to-local, (2) local-to-backplane, (3) backplane- to-backplane, (4) local-to-local, and (5) uni-directional switch. the following sections describe the switching paths. the switch paths of configurations (1) to (4) may be operated simultaneously and in all 5 cases the backplane streams may be operated at a fixed data-rate of 32.768 mb/s on 16 input and 16 output streams, or optionally, at 16.384 mb/s or lower data-rates on 32 input and 32 output streams. the local streams (16 input and 16 output) may be operated at 16.384 mb/s or lower data-ra tes. when the lower data-rates of 8.192, 4.096, and MT90870 6 k by 6 k bsti24-31 lsti0-15 6 k by 6 k bsto24-31 lsto0-15 bsti0-23 bsto0-23 6 k by 6 k 6 k by 6 k total 24 input streams and 24 output streams total 24 input streams and 24 output streams MT90870 data sheet 20 zarlink semiconductor inc. 2.048 mb/s are included, there will be a corresponding reduction in switch capacity although conversion between differing rates will be maintained. 2.1.1 backplane-to-local path the device can provide data switching between the backpla ne input port (8192 channels) and the local output port (4096 channels). the local connection memory determines the switching configurations. 2.1.2 local-to-backplane path the device can provide data switching between the local input port (4096 channels) and the backplane output port (8192 channels). the backplane connection memory determines the switching configurations. 2.1.3 backplane-to-backplane path the device can provide data switching between the back plane input (8192 channels) and output (8192 channels) ports. the backplane connection memory de termines the switch ing configurations. 2.1.4 local-to-local path the device can provide data switching between the local input (4096 channels) and ou tput (4096 channels) ports. the local connection memory determi nes the switching configurations. 2.1.5 uni-directional switch the device may be optionally conf igured to provide a 12,288 x 12,288 uni-d irectional switch by grouping together backplane and local input and output streams. 2.2 port data rate modes and selection the selection of individual stream data-rates is summarized in table 1. 2.2.1 local port rate selection the local port has 16 input (lsti0-15) and 16 output (l sto0-15) data streams. all input and output streams may be individually selected for operation at a data rate of either 2.048 mb/s, 4.096 mb/s, 8.192 mb/s or 16.384 mb/s. the timing of the input and output cloc ks and frame pulses are shown in figu re 6, local port timing diagram for 2,4,8 and 16 mb/s stream rates. 2.2.1.1 local input port the bit rate for each input stream is selected by writing to a dedicated local input bit rate register (librr0-15). refer to table 41, local input bit rate register (librrn) bits. stream number rate selection capability (for each individual stream) input stream - backplane 0-15 (bsti0-15) 2.048, 4.096, 8.192 or 16.384 mb/s - non-32 mb/s mode 32.768 mb/s - 32 mb/s mode input stream - backplane 16-31 (bsti16-31) 2.048, 4.096, 8.192 or 16.384 mb/s - non-32 mb/s mode unused - 32 mb/s mode output stream - backplane 0-15 (bsto0-15) 2.048, 4.096, 8.192 or 16.384 mb/s - non-32 mb/s mode 32.768 mb/s - 32 mb/s mode MT90870 data sheet 21 zarlink semiconductor inc. table 1 - per-stream data-rate selection: backplane and local, non-32 mb/s mode and 32 mb/s mode figure 6 - local port timing diagram for 2,4,8 and 16 mb/s stream rates output stream - backplane 16-31 (bsto16-31) 2.048, 4.096, 8.192 or 16.384 mb/s - non-32 mb/s mode unused - 32 mb/s mode input stream - local 0-15 (lsti0- 15) 2.048, 4.096, 8.192 or 16.384 mb/s output stream - local 0-15 (lsto0- 15) 2.048, 4.096, 8.192 or 16.384 mb/s stream number rate selection capability (for each individual stream) fp8i (st-bus) (8.192 mhz) c8i (gci) (8 khz) (8 khz) fp8i (gci) (8.192 mhz) c8i (st-bus) 7 2 3 4 5 610 0 lsti/lsto0-15 (16 mb/s) st 1 2 3 4 5 610 7 channel 255 channel 0 0 lsti/lsto0-15 (8 mb/s) gci channel 0 3 7 6 channel 127 5 4 7 lsti/lsto0-15 (4 mb/s) st channel 0 6 0 1 channel 63 7 12 7 0 0 0 lsti/lsto0-15 (2 mb/s) gci channel 0 7 channel 31 0 7 0 5 4 3 2 167 7 lsti/lsto0-15 (16 mb/s) gci 6 5 4 3 2 167 0 channel 255 channel 0 7 lsti/lsto0-15 (8 mb/s) st channel 0 4 0 1 channel 127 2 3 65 0 7 0 lsti/lsto0-15 (4 mb/s) gci channel 0 1 7 6 channel 63 0 7 7 lsti/lsto0-15 (2 mb/s) st channel 0 0 channel 31 7 0 MT90870 data sheet 22 zarlink semiconductor inc. 2.2.1.2 local output port the bit rate for each output stream is selected by writi ng to a dedicated local output bit rate register (lobrr0- 15). refer to table 43, local output bit rate register (lobrrn) bits. operation of stream data in the conne ction mode or the message mode is det ermined by the state of the lmm bit, and the channel high-impedance state is controlled by the le bit of the local connection memory. the data source (i.e. from the local or backplane data memory) is determined by the lsrc bit of the local connection memory. refer to section 6.1, local connection memory, and se ction 12.3, local connection memory bit definition. 2.2.2 backplane port rate selection the backplane streams may be operated in one of tw o modes, namely non-32 mb/s mode and 32 mb/s mode. the local stream data-rates are not affected by the oper ating mode of the backplane. the operating mode of the backplane is determined by setting the control register bit, mode32. setti ng the bit high will invoke the 32 mb/s mode. setting the bit low will invoke the non-32 mb/s mo de. the default bit value on device reset is low. the timing of the input and output cloc ks and frame pulses are shown in figure 7, backplane port timing diagram for 2, 4, 8, 16 and 32 mb/s stream rates. non-32 mb/s mode: each of the 32 backplane streams (bsti0-31 and bsto0-31) and local streams (lsti0-15 and lsto0-15) can be independently programmed for a dat a-rate of 2.048 mb/s, 4.096 mb/s, 8.192 mb/s or 16.384 mb/s. 32 mb/s mode: 16 of the backplane input streams (bst i0-15) and 16 backplane out put (bsto0-15) streams operate at a fixed rate of 32.768 mb/s. in this mode, the upper 16 input (bsti16-31) and 16 output (bsti16-31) streams are unused. all 32 local streams can be indep endently programmed for a data-rate of 2.048 mb/s, 4.096 mb/s, 8.192 mb/s or 16.384 mb/s. 2.2.2.1 backplane input port the bit rate for each input stream is selected by writi ng to a dedicated backplane input bit rate register (bobrr0- 31). refer to table 45, backplane input bit rate register (bibrrn) bits. if the 32 mb/s mode is selected by writing to the control register bit (mode32), the settings in bibrrn are ignored. 2.2.2.2 backplane output port the bit rate for each output stream is selected by writ ing to a dedicated backplane output bit rate register (bobrr0-31). refer to table 47, backplane output bit rate register (bobrrn) bits. if the 32 mb/s mode is selected by writing to the control register bit (mode32), the settings in bobrrn are ignored. operation of stream data in the connec tion mode or the message mode is dete rmined by the state of the bmm bit, and the channel high-impedance state is controlled by the be bit of the backplane connection memory. the data source (i.e., from the local or backplane data me mory) is determined by the bsrc bit of the backplane connection memory. refer to section 6.2, backpl ane connection memory and section 12.4, backplane connection memory bit definition. MT90870 data sheet 23 zarlink semiconductor inc. figure 7 - backplane port timing diagram for 2, 4, 8, 16 and 32 mb/s stream rates 2.3 backplane frame pulse input and master input clock timing the backplane frame pulse (fp8i ) is an 8 khz input signal active for 122 ns or 244 ns at the frame boundary. the fpw bit in the control register must be set according to the applied pulse width. see pin description and table 16, control register bits, for details. the active state and timing of fp8i may conform either to the st-bus or to the gci-bus as shown in figure 6, local port timing diagram for 2,4,8 and 16 mb/s stream ra tes, and figure 7, backplane port timing diagram for 2, 4, 8, 16 and 32 mb/s stream rates. the mt90869 will automa tically detect whether an st-bus or a gci-bus style frame pulse is being used for the master frame pulse (fp8i ). the device will detect the frame boundary alignment using the rising edge of the input clock (c8i ), provided the c8ipol bit in t able 16, ?control register bits,? on page 52 is set to one. before the c8ipol bit is set to one, the frame boundary will not be detected correctly. for the fp8i (st-bus) (8.192 mhz) 7 2 3 4 5 610 0 bsti/bsto0-31 (16 mb/s) st 1 2 3 4 5 610 7 channel 255 channel 0 c8i (gci) 0 bsti/bsto0-31 (8 mb/s) gci channel 0 3 7 6 channel 127 5 4 (8 khz) (8 khz) fp8i (gci) 7 bsti/bsto0-31 (4 mb/s) st channel 0 6 0 1 channel 63 7 12 7 7 2 3 4 5 6 10 bsti/bsto0-15 (32 mb/s) st channel 0 72 3 4 5 610 channel 1 2 310 7 2 3 4 5 6 10 channel 511 2 3 4 5 610 channel 510 76 0 0 (8.192 mhz) c8i (st-bus) 0 bsti/bsto0-31 (2 mb/s) gci channel 0 7 channel 31 0 7 0 5 4 3 2 1 67 bsti/bsto0-15 (32 mb/s) gci channel 0 05 4 3 2 167 channel 1 5 467 05 4 3 2 167 channel 511 5 4 3 2 167 channel 510 01 0 5 4 3 2 167 7 bsti/bsto0-31 (16 mb/s) gci 6 5 4 3 2 167 0 channel 255 channel 0 7 bsti/bsto0-31 (8 mb/s) st channel 0 4 0 1 channel 127 2 3 65 0 7 0 bsti/bsto0-31 (4 mb/s) gci channel 0 1 7 6 channel 63 0 7 7 bsti/bsto0-31 (2 mb/s) st channel 0 0 channel 31 7 0 MT90870 data sheet 24 zarlink semiconductor inc. purposes of describing the device operat ion, the remaining part of this doc ument assumes the st-bus style frame pulse with a single width frame pulse of 122 ns and the c8 ipol bit is set to one unless explicitly stated otherwise. in addition, the device provides fp8o , fp16o , c8o and c16o outputs to support external devices which connect to the local port. the local frame pulses (fp8o , fp16o ) will be provided in the same style as the master frame pulse (fp8i ). the polarity of c8o and c16o , at the frame boundary, can be cont rolled by the control register bit, copol. an analogue phase lock loop (apll) is used to multiply the external clock frequency to generate an internal clock signal operated at 131.072 mhz. 2.4 backplane frame pulse input and local frame pulse output alignment the MT90870 accepts a backplane frame pulse (fp8i ) and generates the local frame pulse outputs, fp8o and fp16o , which are aligned to the master frame pulse. there is a constant three frame delay for data being switched. figure 8, backplane and local frame pulse alignment for data rates of 2 mb/s, 4 mb/s, 8 mb/s and 16 mb/s, shows the backplane and local frame pulse alignment for different data rates. for further details of frame pulse c onditions and options see section 13 .1, control register (cr), figure 18, frame boundary conditions, st- bus operation, an d figure 19, frame boundary conditions, gci - bus operation. figure 8 - backplane and local frame pulse ali gnment for data rates of 2 mb/s, 4 mb/s, 8 mb/s and 16 mb/s 3.0 input and output offset programming 3.1 input channel delay programming (backplane and local input streams) various registers are used to control the input sampling point (delay) and th e output advancement for the local and backplane streams. the following sections explain the details of these offs et programming features. the control of the input channel delay and the input bit delay allows each input stream to have a different frame boundary with respect to the master frame pulse, fp8i . by default, all input stream s have channel delay of zero such that ch0 is the first channel that appears after the frame boundary. ch3 ch7 ch0 ch1 ch2 bsti/bsto0-31 (16 mb/s) c8o fp8o lsti/lsto0-15 (2 mb/s) lsti/lsto0-15 (4 mb/s) lsti/lsto0-15 (8 mb/s) lsti/lsto0-15 (16 mb/s) ch2 ch1 ch0 ch6 ch5 ch4 ch3 ch2 ch0 ch4 ch5 ch10 ch9 ch8 ch11 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 ch 19 ch 18 ch 17 ch 16 ch 23 ch 22 ch 21 ch 20 ch1 ch 3 ch 2 ch 1 ch 0 ch 7 ch 6 ch 5 ch 4 ch 11 ch 10 ch 9 ch 8 ch 15 ch 14 ch ch 12 13 ch 17 ch 16 ch 21 ch 20 ch ch 18 19 ch 23 ch 22 fp8i c8i ch3 ch7 ch0 ch1 ch2 (2 mb/s) bsti/bsto0-31 (4 mb/s) bsti/bsto0-31 ch2 ch1 ch0 ch6 ch5 ch4 ch3 ch2 ch0 ch4 ch5 ch10 ch9 ch8 ch11 ch1 bsti/bsto0-31 (8 mb/s) MT90870 data sheet 25 zarlink semiconductor inc. by programming the backplan e or local input channel delay registers, bcdr0-31 and lcdr0-15, users can assign the ch0 position to be located at any one of the channel boundaries in a frame. see figure 9. figure 9 - backplane and local input channel delay timing diagram (8 mb/s) for delays within channel boundaries, the input bit delay programming c an be used. the use of input channel delay in combination with input bit delay enables the c h0 position to be placed anywhere within a frame to a resolution of 1/4 of the bit period. 3.2 input bit delay programming (backplane and local input streams) in addition to the input channel dela y programming, the input bi t delay programming feature provides users with greater flexibility when desi gning switch matrices for high speed operati on. the input bit delay may be programmed on a per-stream basis to accommodate delays created on pc m highways. for all streams the delay is up to 7 3/4 bits with a resolution of 1/4 bit, for the selected data-rate. see figure 10 and figure 11 for input bit delay timing at 16 mb/s and 8 mb/s data rates, respectively. the local input delay is defined by the local input dela y registers, lidr0 to lidr1 5, corresponding to the local data streams, lsti0 to lsti15, and the backplane input delay is defined by the backplane input delay registers, bidr0 to bidr31, which correspond to the backplane data streams, bsti0 to bsti31. fp8 i c8 i 72 3 4 5 610 bsti0-31/lsti0-15 channel delay = 0 ch 0 72 3 4 5 610 ch 1 2 310 72 3 4 5 610 ch127 2 3 4 5 610 ch126 76 72 3 4 5 610 bsti0-31/lsti0-15 channel delay = 1 ch127 72 3 4 5 610 ch 0 2 310 72 3 4 5 610 ch126 2 3 4 5 610 ch125 76 72 3 4 5 610 bsti0-31lsti0-15 channel delay = 2 ch127 72 3 4 5 610 ch127 2 310 72 3 4 5 610 ch125 2 3 4 5 610 ch0 76 (default) channel delay,1 channel delay, 2 7 MT90870 data sheet 26 zarlink semiconductor inc. figure 10 - backplane and local input bit delay timing diagram for data rate of 16 mb/s c8 i 72 3 4 5 610 bsti0-31/lsti0-15 bit delay = 0 ch0 74 5 6 ch1 2 310 bsti0-31/lsti0-15 bit delay = 1/4 72 3 4 5 610 bsti0-31/lsti0-15 bit delay = 1 ch0 75 6 ch1 2 310 (default) 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch255 ch255 ch255 bit delay, 1/4 bit delay, 1 bsti0-31/lsti0-15 bit delay = 1/2 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch255 bit delay, 1/2 bsti0-31/lsti0-15 bit delay = 3/4 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch255 bit delay, 3/4 bsti0-31/lsti0-15 bit delay = 7 1/2 72 3 4 5 610 ch255 74 5 6 ch0 210 ch254 bit delay, 7 1/2 bsti0-31/lsti0-15 bit delay = 7 3/4 72 3 4 5 610 ch255 74 5 6 ch0 210 ch254 bit delay, 7 3/4 fp8 i MT90870 data sheet 27 zarlink semiconductor inc. figure 11 - backplane and local input bit de lay timing diagram for data rate of 8 mb/s 3.3 output advancement programming (backplane and local output streams) this feature is used to advance the output channel alignment of individual local or back plane output streams with respect to the frame boundary. each output stream has its own advancement value which can be programmed by the output advancement regist ers. the output advancement selection is useful in compensating for various parasitic loading on the serial data output pins. 3.3.1 local output advancement programming the local output advanc ement registers, loar0-15 , are used to control the local output advancement. the advancement is determined with reference to the inter nal system clock rate (131.072 mhz). for 2 mb/s, 4 mb/s, 8 mb/s or 16 mb/s streams the advancement may be 0, -2 cycles, -4 cycles or -6 cycles, which converts to approximately 0ns, -15 ns, -30 ns or -45 ns as shown in figure 12. 3.3.2 backplane output advancement programming the backplane output advancement registers, boar0-31 are used to control the backplane output advancement. the advancement is determined with reference to the internal system clock ra te (131.072 mhz). for 2 mb/s, 4 mb/s, 8 mb/s or 16 mb/s streams the ad vancement may be 0, -2 cycles, -4 cycles or -6 cycles, which converts to c8 i 72 3 4 5 610 bsti0-31/lsti0-15 bit delay = 0 ch0 74 5 6 ch1 2 310 bsti0-31/lsti0-15 bit delay = 1/4 72 3 4 5 610 bsti0-31/lsti0-15 bit delay = 1 ch0 75 6 ch1 2 310 (default) 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch127 ch127 ch127 bit delay, 1/4 bit delay, 1 bsti0-31/lsti0-15 bit delay = 1/2 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch127 bit delay, 1/2 bsti0-31/lsti0-15 bit delay = 3/4 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch127 bit delay, 3/4 bsti0-31/lsti0-15 bit delay = 7 1/2 72 3 4 5 610 ch127 74 5 6 ch0 210 ch126 bit delay, 7 1/2 bsti0-31/lsti0-15 bit delay = 7 3/4 72 3 4 5 610 ch127 74 5 6 ch0 210 ch126 bit delay, 7 3/4 fp8 i MT90870 data sheet 28 zarlink semiconductor inc. approximately 0ns, -15 ns, -30 ns or -45 ns as shown in figure 12. for 32 mb/s str eams, the advancement may be 0, -1 cycle, -2 cycles or -3 cycles, which co nverts to approximately 0ns, -7 ns, -15 ns or -22 ns. figure 12 - backplane and local output advanc ement timing diagram for data rate of 16 mb/s 4.0 port high impedance control 4.1 local port high impedance control the input pin, lors , selects whether the local output streams, lsto0-15 are set to high impedance at the output of the MT90870 itself, or are always dr iven (active high or active low) and a high impedance state, if required on a per-channel basis, is invoked through an ex ternal interface circuit controlled by the lcsto0-1 signals. setting lors to a low state will conf igure the output streams, lsto0-15, to transmit bi-state channel data with per- channel high-impedance determined by extern al circuits under the control of the lcsto0-1 outputs. setting lors to a high state will conf igure the output streams, lsto0-15, of the MT90870 to invoke a high-impedance output on a per-channel basis. the lors pin is an asynchronous input and is expected to be hard-wired for a particular system application, although it may be driven under logic control if preferred. 4.1.1 lors set low the data (channel control bit) transmitted by lcsto0-1 replicates the local output enable bit ( le ) of the local connection memory, with a low state indicating the channel to be set to high impedance. see section 12.3, local connection memory bit definition for se tting the local output enable bit ( le ). the lcsto0-1 outputs transmit serial data (channel control bits) at 16.384 mb/s, with each bit representing the per- channel high impedance state for specific streams. eight output streams are allocated to each control line as follows: (see also pin description ) ? lcsto0 outputs the channel control bits for streams: lsto0, 2, 4, 6, 8, 10, 12, and 14. ? lcsto1 outputs the channel control bits for streams: lsto1, 3, 5, 7, 9, 11, 13, and 15. the channel control bit location, within a frame period, for each channel of the local output streams is presented in table 2, lcsto allocation of channel cont rol bits to the output streams. bit advancement, -2 bit advancement, -4 bit advancement, -6 fp8o system clock bsto0-31 /lsto0-15 bit advancement = 0 bsto0-31 /lsto0-15 bit advancement = -2 (default) bit advancement = -6 bsto0-31 /lsto0-15 bit advancement = -4 bsto0-31 /lsto0-15 131.072 mhz ch255 ch255 ch255 ch255 ch0 ch0 ch0 ch0 bit 1 bit 0 bit 7 bit 6 bit 5 bit 1 bit 0 bit 7 bit 6 bit 5 bit 1 bit 0 bit 7 bit 6 bit 5 bit 1 bit 0bit 7bit 6bit 5 bit 4 bit 4 MT90870 data sheet 29 zarlink semiconductor inc. as an aid to the description, the channel control bit for a single channel on specific streams is presented, with reference to table 2: (1) the channel control bit corresponding to stream 0, channel 0, lsto0_ch0, is transmitted on lcsto0 and is advanced, relative to the fram e boundary, by 10 periods of c16o . (2) the channel control bit corresponding to stream 14, channel 0, lsto14_ch0, is transmitted on lcsto0 in advance of the frame boundary by three periods of output clock, c16o . similarly, the channel control bit for lsto15_ch0 , is advanced relative to the frame boundary by three periods of c16o , on lcsto1 . the lcsto0-1 outputs data at a constant data-rate of 16.384 mb /s, independent of the data-rate selected for the individual output streams, lsto0-15 . streams at data-rates lower than 16. 384 mb/s will have the value of the respective channel control bit repeated for the duration of the channel. the bit will be repeated twice for 8.192 mb/s streams, four times for 4.096 mb/s streams and eight time s for 2.048 mb/s streams. the channel control bit is not repeated for 16.384 mb/s streams. examples are presented, with reference to table 2: (3) with stream lsto4 selected to operate at a data-rate of 2. 048 mb/s, the value of the channel control bit for channel 0 will be transmitted during the c16o clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and 48. (4) with stream lsto8 operated at a data-rate of 8.192 mb/s, the value of the channel control bit for channel 1 will be transmitted during the c16o clock period nos. 9 and 17. figure 13, local port external high impedance control bit timing (st-bus mode) shows the channel control bits for lcsto0 and lcsto1 in one possible scenario which includes stream lsto0 at a data-rate of 16.384 mb/s, lsto1 at 8.192 mb/s, lsto6 at 4.096 mb/s and lsto7 at 2.048 mb/s. all remaining streams are operated at a data-rate of 16.384 mb/s. 4.1.2 lors set high the local output enable bit ( le ) of the local connection memory has direct per-channel control on the high- impedance state of the lo cal output streams, lsto0-15 . programming the le bit to a low state will set the stream output of the MT90870 to high impedance for the dur ation of the channel period . see section 12.3, local connection memory bit definiti on, for programming details. the lcsto0-1 outputs remain active. allocated stream no. allocated channel no. 2 c16o period 1 lcsto0 lcsto1 16 mb/s 8 mb/s 4 mb/s 2 mb/s 2039 0 3-1 1 ch 0 ch 0 ch 0 ch 0 2040 2 3-3 3 ch 0 ch 0 ch 0 ch 0 2041 4 5 ch 0 ch 0 ch 0 ch 0 2042 6 7 ch 0 ch 0 ch 0 ch 0 2043 8 9 ch 0 ch 0 ch 0 ch 0 2044 10 11 ch 0 ch 0 ch 0 ch 0 2045 12 13 ch 0 ch 0 ch 0 ch 0 2046 14 3-2 15 3-2 ch 0 ch 0 ch 0 ch 0 table 2 - lcsto allocation of channel control bits to the output streams MT90870 data sheet 30 zarlink semiconductor inc. 2047 0 1 ch 1 ch 0 ch 0 ch 0 2048 2 3-3 3 ch 1 ch 0 ch 0 ch 0 frame 1 4 5 ch 1 ch 0 ch 0 ch 0 boundary 2 6 7 ch 1 ch 0 ch 0 ch 0 3 8 9 ch 1 ch 0 ch 0 ch 0 4 10 11 ch 1 ch 0 ch 0 ch 0 5 12 13 ch 1 ch 0 ch 0 ch 0 6 14 15 ch 1 ch 0 ch 0 ch 0 7 0 1 ch 2 ch 1 ch 0 ch 0 82 3-3 3 ch 2 ch 1 ch 0 ch 0 94 3-4 5 ch 2 ch 1 ch 0 ch 0 10 6 7 ch 2 ch 1 ch 0 ch 0 11 8 9 ch 2 ch 1 ch 0 ch 0 12 10 11 ch 2 ch 1 ch 0 ch 0 13 12 13 ch 2 ch 1 ch 0 ch 0 14 14 15 ch 2 ch 1 ch 0 ch 0 15 0 1 ch 3 ch 1 ch 0 ch 0 16 2 3-3 3 ch 3 ch 1 ch 0 ch 0 17 4 3-4 5 ch 3 ch 1 ch 0 ch 0 etc etc etc etc etc etc etc etc etc etc etc etc etc etc 2029 etc etc ch 254 ch 127 ch 63 ch 31 2030 14 15 ch 254 ch 127 ch 63 ch 31 2031 0 1 ch 255 ch 127 ch 63 ch 31 2032 2 3 ch 255 ch 127 ch 63 ch 31 2033 4 5 ch 255 ch 127 ch 63 ch 31 2034 6 7 ch 255 ch 127 ch 63 ch 31 2035 8 9 ch 255 ch 127 ch 63 ch 31 2036 10 11 ch 255 ch 127 ch 63 ch 31 2037 12 13 ch 255 ch 127 ch 63 ch 31 2038 14 15 ch 255 ch 127 ch 63 ch 31 2039 0 1 ch 0 ch 0 ch 0 ch 0 allocated stream no. allocated channel no. 2 c16o period 1 lcsto0 lcsto1 16 mb/s 8 mb/s 4 mb/s 2 mb/s table 2 - lcsto allocation of channel control bits to the output streams (continued) MT90870 data sheet 31 zarlink semiconductor inc. note 1: clock period count is referenced to frame boundary. note 2: the channel numbers presented relate to the data-rate selected for a specific stream. note 3-1 to 3-4: see section 4.1.1 for examples of channel control bit for streams of different data-rates. 2040 2 3 ch 0 ch 0 ch 0 ch 0 2041 4 5 ch 0 ch 0 ch 0 ch 0 2042 6 7 ch 0 ch 0 ch 0 ch 0 2043 8 9 ch 0 ch 0 ch 0 ch 0 2044 10 11 ch 0 ch 0 ch 0 ch 0 2045 12 13 ch 0 ch 0 ch 0 ch 0 2046 14 15 ch 0 ch 0 ch 0 ch 0 2047 0 1 ch 1 ch 0 ch 0 ch 0 2048 2 3 ch 1 ch 0 ch 0 ch 0 frame 1 4 5 ch 1 ch 0 ch 0 ch 0 boundary 2 6 7 ch 1 ch 0 ch 0 ch 0 3 8 9 ch 1 ch 0 ch 0 ch 0 etc etc etc etc etc etc etc allocated stream no. allocated channel no. 2 c16o period 1 lcsto0 lcsto1 16 mb/s 8 mb/s 4 mb/s 2 mb/s table 2 - lcsto allocation of channel control bits to the output streams (continued) MT90870 data sheet 32 zarlink semiconductor inc. figure 13 - local port external high impedance control bit timing (st-bus mode) 4.2 backplane high impedance control the input pin, bors , selects whether the backplane output streams, bsto0-31 are set to high impedance at the output of the MT90870 itself, or are always driven (a ctive high or active low) and a high impedance state, if required on a per-channel basis, is invoked through an external interface circuit controlled by the bcsto0-3 signals. setting bors to a low state will configure the output streams, bsto0-31, to transmit bi-state channel data with per-channel high-impedance determined by external circuits u nder the control of the bcsto0-3 outputs. setting bors to a high state will conf igure the output streams, bsto0-31, of the MT90870 to invoke a high- impedance output on a per-channel basis. the bors pin is an asynchronous input and is expected to be hard-wired for a particular system application, although it may be driven under logic control if preferred. 4.2.1 bors set low, non-32 mb/s mode the data (channel control bit) transmitted by bcsto0-3 replicates the backplane output enable bit ( be ) of the backplane connection memory, with a low state indicati ng the channel to be set to high impedance. see section 12.4, backplane connection memory bit definition for setting the backpl ane output enable bit ( be ). chan 0 bit 7 chan 0 bit 6 chan 63 bit 1 chan 63 bit 0 chan 0 bit 7 chan 63 bit 0 7 6 5 4 3 2 3 2 1 0 5 4 1 6 0 7 7 6 0 chan 0 bit 7 chan 0 bit 6 chan 0 bit 5 chan 0 bit 4 chan 127 bit 3 chan 127 bit 2 chan 127 bit 1 chan 127 bit 0 chan 0 bit 7 chan 127 bit 0 channel 0 bit 7 channel 31 bit 0 chan 0 bit 7 chan 31 bit 0 lcsto0 lsto0 (16 mb/s) lsto1 (8 mb/s) lsto6 (4 mb/s) lsto7 (2 mb/s) c8o fp8o ch 1 lsto0 ch 1 lsto2 ch 1 lsto4 ch 1 lsto6 ch 1 lsto8 ch 1 lsto10 ch 1 lsto12 ch 1 lsto14 ch 2 lsto0 ch 2 lst02 ch 0 lsto4 ch 0 lsto6 ch 0 lsto8 ch 0 lsto10 ch 0 lsto12 ch 0 lsto14 ch 1 lsto0 ch 1 lsto2 ch 1 lsto4 ch 1 lsto6 ch 1 lsto1 ch 1 lsto3 ch 1 lsto5 ch 1 lsto7 ch 1 lsto9 ch 1 lsto11 ch 1 lsto13 ch 1 lsto15 ch 1 lsto1 ch 2 lsto3 ch 0 lsto5 ch 0 lsto7 ch 0 lsto9 ch 0 lsto11 ch 0 lsto13 ch 0 lsto15 ch 0 lsto1 ch 1 lsto3 ch 1 lsto5 ch 1 lsto7 lcsto1 one c16o period channel 0 channel 255 bits 7-0 1 MT90870 data sheet 33 zarlink semiconductor inc. the bcsto0-3 outputs transmit serial data (channel control bits) at 16.384 mb/s, with each bit representing the per- channel high impedance state for specific streams. eight output streams are allocated to each control line as follows: (see also pin description ) ? bcsto0 outputs the channel control bits for streams bsto0, 4, 8, 12, 16, 20, 24 and 28. ? bcsto1 outputs the channel control bits for streams bsto1, 5, 9, 13, 17, 21, 25 and 29. ? bcsto2 outputs the channel control bits for streams bsto2, 6, 10, 14, 18, 22, 26 and 30. ? bcsto3 outputs the channel control bits for streams bsto3, 7, 11, 15, 19, 23, 27 and 31. the channel control bit location, within a frame period , for each channel of t he backplane output streams is presented in table 3, bcsto allocation of channel control bits to the output streams (non-32 mb/s mode) . as an aid to the description, the channel control bit for a single channel on specific streams is presented, with reference to table 3: (1) the channel control bit corresponding to stream 0, channel 0, bsto0_ch0, is transmitted on bcsto0 and is advanced, relative to the fram e boundary, by 10 periods of c16o . (2) the channel control bit corresp onding to stream 28, channel 0, bsto28_ch0, is transmitted on bcsto0 in advance of the frame boundary by three periods of output clock, c16o . similarly, the channel control bits for bsto29_ch0 , bsto30_ch0 and bsto31_ch0 are advanced relative to the frame boundary by three periods of c16o , on bcsto1 , bcsto2 and bcsto3 , respectively. the bcsto0-3 outputs data at a constant data-rate of 16.384 mb/s , independent of the data-rate selected for the individual output streams, bsto0-31 . streams at data-rates lower than 16.384 mb/s will have the value of the respective channel control bit repeated for the duration of the channel. the bit will be repeated twice for 8.192 mb/s streams, four times for 4.096 mb/s streams and eight time s for 2.048 mb/s streams. the channel control bit is not repeated for 16.384 mb/s streams. examples are presented, with reference to table 3: (3) with stream bsto4 selected to operate at a data-rate of 2.048 mb/s, the value of the channel control bit for channel 0 will be transmitted during the c16o clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and 48. (4) with stream bsto8 operated at a data-rate of 8.192 mb/s, the value of the channel control bit for channel 1 will be transmitted during the c16o clock period nos. 9 and 17. allocated stream no. channel no. 2 c16o period 1 bcsto0 bcsto1 bcsto2 bcsto3 16 mb/s 8 mb/s 4 mb/s 2 mb/s 2039 0 3-1 1 2 3 ch 0 ch 0 ch 0 ch 0 2040 4 3-3 5 6 7 ch 0 ch 0 ch 0 ch 0 2041 8 9 10 11 ch 0 ch 0 ch 0 ch 0 2042 12 13 14 15 ch 0 ch 0 ch 0 ch 0 2043 16 17 18 19 ch 0 ch 0 ch 0 ch 0 2044 20 21 22 23 ch 0 ch 0 ch 0 ch 0 2045 24 25 26 27 ch 0 ch 0 ch 0 ch 0 2046 28 3-2 29 3-2 30 3-2 31 3-2 ch 0 ch 0 ch 0 ch 0 table 3 - bcsto allocation of channel control bits to the output streams (non-32 mb/s mode) MT90870 data sheet 34 zarlink semiconductor inc. 2047 0 1 2 3 ch 1 ch 0 ch 0 ch 0 2048 4 3-3 5 6 7 ch 1 ch 0 ch 0 ch 0 frame 1 8 9 10 11 ch 1 ch 0 ch 0 ch 0 boundary 2 12 13 14 15 ch 1 ch 0 ch 0 ch 0 3 16 17 18 19 ch 1 ch 0 ch 0 ch 0 4 20 21 22 23 ch 1 ch 0 ch 0 ch 0 5 24 25 26 27 ch 1 ch 0 ch 0 ch 0 6 28 29 30 31 ch 1 ch 0 ch 0 ch 0 7 0 1 2 3 ch 2 ch 1 ch 0 ch 0 8 4 3-3 5 6 7 ch 2 ch 1 ch 0 ch 0 9 8 3-4 9 10 11 ch 2 ch 1 ch 0 ch 0 10 12 13 14 15 ch 2 ch 1 ch 0 ch 0 11 16 17 18 19 ch 2 ch 1 ch 0 ch 0 12 20 21 22 23 ch 2 ch 1 ch 0 ch 0 13 24 25 26 27 ch 2 ch 1 ch 0 ch 0 14 28 29 30 31 ch 2 ch 1 ch 0 ch 0 15 0 1 2 3 ch 3 ch 1 ch 0 ch 0 16 4 3-3 5 6 7 ch 3 ch 1 ch 0 ch 0 17 8 3-4 9 10 11 ch 3 ch 1 ch 0 ch 0 etc etc etc etc etc etc etc etc etc etc etc etc etc etc etc etc etc etc 2029 etc etc etc etc ch 254 ch 127 ch 63 ch 31 2030 28 29 30 31 ch 254 ch 127 ch 63 ch 31 2031 0 1 2 3 ch 255 ch 127 ch 63 ch 31 2032 4 5 6 7 ch 255 ch 127 ch 63 ch 31 2033 8 9 10 11 ch 255 ch 127 ch 63 ch 31 2034 12 13 14 15 ch 255 ch 127 ch 63 ch 31 2035 16 17 18 19 ch 255 ch 127 ch 63 ch 31 2036 20 21 22 23 ch 255 ch 127 ch 63 ch 31 2037 24 25 26 27 ch 255 ch 127 ch 63 ch 31 2038 28 29 30 31 ch 255 ch 127 ch 63 ch 31 2039 0 1 2 3 ch 0 ch 0 ch 0 ch 0 2040 4 5 6 7 ch 0 ch 0 ch 0 ch 0 2041 8 9 10 11 ch 0 ch 0 ch 0 ch 0 2042 12 13 14 15 ch 0 ch 0 ch 0 ch 0 allocated stream no. channel no. 2 c16o period 1 bcsto0 bcsto1 bcsto2 bcsto3 16 mb/s 8 mb/s 4 mb/s 2 mb/s table 3 - bcsto allocation of channel control bits to the output streams (non-32 mb/s mode) (continued) MT90870 data sheet 35 zarlink semiconductor inc. note 1: clock period count is referenced to frame boundary. note 2: the channel numbers presented relate to the data-rate selected for a specific stream. note 3-1 to 3-4: see section 4.2.1 for examples of channel control bit for streams of different data-rates. 2043 16 17 18 19 ch 0 ch 0 ch 0 ch 0 2044 20 21 22 23 ch 0 ch 0 ch 0 ch 0 2045 24 25 26 27 ch 0 ch 0 ch 0 ch 0 2046 28 29 30 31 ch 0 ch 0 ch 0 ch 0 2047 0 1 2 3 ch 1 ch 0 ch 0 ch 0 2048 4 5 6 7 ch 1 ch 0 ch 0 ch 0 frame 1 8 9 10 11 ch 1 ch 0 ch 0 ch 0 boundary 2 12 13 14 15 ch 1 ch 0 ch 0 ch 0 3 16 17 18 19 ch 1 ch 0 ch 0 ch 0 etc etc etc etc etc etc etc etc etc allocated stream no. channel no. 2 c16o period 1 bcsto0 bcsto1 bcsto2 bcsto3 16 mb/s 8 mb/s 4 mb/s 2 mb/s table 3 - bcsto allocation of channel control bits to the output streams (non-32 mb/s mode) (continued) MT90870 data sheet 36 zarlink semiconductor inc. figure 14 - backplane port external high impedance control bit timing (non-32 mb/s mode) figure 14, backplane port external high impedance co ntrol bit timing (non-32 mb/s mode) shows the channel control bits for bcsto0 , bcsto1 , bcsto2 and bcsto3 in one possible scenario which includes stream bsto0 at a data-rate of 16.384 mb/s, bsto1 at 8.192 mb/s, bsto6 at 4.096 mb/s and bsto7 at 2.048 mb/s. all remaining streams are operated at a data-rate of 16.384 mb/s. 4.2.2 bors set low, 32 mb/s mode the data (channel control bit) transmitted by bcsto0-3 replicates the backplane output enable bit ( be ) of the backplane connection memory, with a low state indica ting the channel be set to high impedance. see section 12.4, backplane connection memory bit definition for setting the backpl ane output enable bit ( be ). chan 0 bit 7 chan 0 bit 6 chan 63 bit 1 chan 63 bit 0 chan 0 bit 7 chan 63 bit 0 7 6 5 4 3 2 3 2 1 0 5 4 1 6 0 7 7 6 0 chan 0 bit 7 chan 0 bit 6 chan 0 bit 5 chan 0 bit 4 chan 127 bit 3 chan 127 bit 2 chan 127 bit 1 chan 127 bit 0 chan 0 bit 7 chan 127 bit 0 channel 0 bit 7 channel 31 bit 0 chan 0 bit 7 chan 31 bit 0 bcsto0 bsto0 (16 mb/s) bsto1 (8 mb/s) bsto6 (4 mb/s) bsto7 (2 mb/s) c8o fp8o ch 1 bsto0 ch 1 bsto4 ch 1 bsto8 ch 1 bsto12 ch 1 bsto16 ch 1 bsto20 ch 1 bsto24 ch 1 bsto28 ch 2 bsto0 ch 1 bst04 ch 0 bsto8 ch 0 bsto12 ch 0 bsto16 ch 0 bsto20 ch 0 bsto24 ch 0 bsto28 ch 1 bsto0 ch 1 bsto4 ch 1 bsto8 ch 1 bsto12 ch 0 bsto1 ch 1 bsto5 ch 1 bsto9 ch 1 bsto13 ch 1 bsto17 ch 1 bsto21 ch 1 bsto25 ch 1 bsto29 ch 1 bsto1 ch 1 bsto5 ch 0 bsto9 ch 0 bsto13 ch 0 bsto17 ch 0 bsto21 ch 0 bsto25 ch 0 bsto29 ch 0 bsto1 ch 1 bsto5 ch 1 bsto9 ch 1 bsto13 ch 1 bsto2 ch 1 bsto0 ch 1 bsto10 ch 1 bsto14 ch 1 bsto18 ch 1 bsto22 ch 1 bsto26 ch 1 bsto30 ch 1 bsto2 ch 0 bsto6 ch 0 bsto10 ch 0 bsto14 ch 0 bsto18 ch 0 bsto22 ch 0 bsto26 ch 0 bsto30 ch 1 bsto2 ch 0 bsto6 ch 1 bsto10 ch 1 bsto14 ch 1 bsto3 ch 0 bsto7 ch 1 bsto11 ch 1 bsto15 ch 1 bsto19 ch 1 bsto23 ch 1 bsto27 ch 1 bsto31 ch 1 bsto3 ch 0 bsto7 ch 0 bsto11 ch 0 bsto15 ch 0 bsto19 ch 0 bsto23 ch 0 bsto27 ch 0 bsto31 ch 1 bsto3 ch 0 bsto7 ch 1 bsto11 ch 1 bsto15 bcsto1 bcsto2 bcsto3 one c16o period channel 0 channel 255 bits 7-0 ch 0 bsto 7 1 MT90870 data sheet 37 zarlink semiconductor inc. the bcsto0-3 outputs transmit serial data (channel control bits) at 16.384 mb/s, with each bit representing the per- channel high impedance state for specific streams. four output streams are allocated to each control line as follows: ? (see also pin description ) ? bcsto0 outputs the channel control bits for streams bsto0, 4, 8, and 12. ? bcsto1 outputs the channel control bits for streams bsto1, 5, 9, and 13. ? bcsto2 outputs the channel control bits for streams bsto2, 6, 10, and 14. ? bcsto3 outputs the channel control bits for streams bsto3, 7, 11, and 15. the channel control bit location, within a frame period , for each channel of t he backplane output streams is presented in table 4, bcsto allocation of channel control bits to the output streams (32 mb/s mode) the bcsto0-3 outputs data at a constant data-rate of 16.384 mb/s and all output streams, bsto0-15 , operate at a data-rate of 32.768 mb/s. as an aid to the description, the channel control bit for a single channel on specific streams is presented, with reference to table 4: (1) the channel control bit corresponding to stream 0, channel 0, bsto0_ch0, is transmitted on bcsto0 and is advanced, relative to the frame boundary, by six periods (clock period no. 2043) of c16o . (2) the channel control bit corresponding to stream 12, channel 0, bsto12_ch0, is transmitted on bcsto0 in advance of the frame boundary by three peri ods (clock period no. 2046) of output clock, c16o . similarly, the channel control bits for bsto13_ch0 , bsto14_ch0 and bsto15_ch0 are advanced relative to the frame boundary by three periods of c16o , on bcsto1 , bcsto2 and bcsto3 , respectively. (3) for stream bsto4 the value of the channel control bit for channel 510 will be transmitted during the c16o clock period no. 2036 on bcsto0 . (4) for stream bsto5 the value of the channel control bit for channel 4 will be transmitted during the c16o clock period no. 12 on bcsto1 . figure 15, backplane port external high impedance cont rol timing (32 mb/s mode) shows the channel control bits for bcsto0 , bcsto1 , bcsto2 and bcsto3 . allocated stream no. channel no. 2 c16o period 1 bcsto0 bcsto1 bcsto2 bcsto3 32 mb/s 2039 0 1 2 3 ch 511 2040 4 5 6 7 ch 511 2041 8 9 10 11 ch 511 2042 12 13 14 15 ch 511 2043 0 3-1 123ch 0 2044 4 5 6 7 ch 0 2045 8 9 10 11 ch 0 2046 12 3-2 13 3-2 14 3-2 15 3-2 ch 0 2047 0 1 2 3 ch 1 table 4 - bcsto allocation of channel control bits to the output streams (32 mb/s mode) MT90870 data sheet 38 zarlink semiconductor inc. 2048 4 5 6 7 ch 1 frame 1 8 9 10 11 ch 1 boundary 2 12 131415ch 1 30 123ch 2 44 567ch 2 58 9 1011ch 2 6 12 131415ch 2 70 123ch 3 84 567ch 3 98 9 1011ch 3 10 12 13 14 15 ch 3 110 123ch 4 12 4 5 3-4 67ch 4 13 8 9 10 11 ch 4 14 12 13 14 15 ch 4 150 123ch 5 164 567ch 5 17 8 9 10 11 ch 5 etc etc etc etc etc etc etc etc etc etc etc etc 2029 etc etc etc etc ch 508 2030 12 13 14 15 ch 508 2031 0 1 2 3 ch 509 2032 4 5 6 7 ch 509 2033 8 9 10 11 ch 509 2034 12 13 14 15 ch 509 2035 0 1 2 3 ch 510 2036 4 3-3 567ch 510 2037 8 9 10 11 ch 510 2038 12 13 14 15 ch 510 2039 0 1 2 3 ch 511 allocated stream no. channel no. 2 c16o period 1 bcsto0 bcsto1 bcsto2 bcsto3 32 mb/s table 4 - bcsto allocation of channel control bits to the output streams (32 mb/s mode) (continued) MT90870 data sheet 39 zarlink semiconductor inc. note 1: clock period count is referenced to frame boundary. note 2: the channel numbers presented relate to the specific stream operating at a data-rate of 32.768 mb/s. note 3-1 to 3-4: see section 4.2.2 for examples of channel control bits. 2040 4 5 6 7 ch 511 2041 8 9 10 11 ch 511 2042 12 13 14 15 ch 511 2043 0 1 2 3 ch 0 2044 4 5 6 7 ch 0 2045 8 9 10 11 ch 0 2046 12 13 14 15 ch 0 2047 0 1 2 3 ch 1 2048 4 5 6 7 ch 1 frame 1 8 9 10 11 ch 1 boundary 2 12 131415ch 1 30 123ch 2 etc etc etc etc etc etc allocated stream no. channel no. 2 c16o period 1 bcsto0 bcsto1 bcsto2 bcsto3 32 mb/s table 4 - bcsto allocation of channel control bits to the output streams (32 mb/s mode) (continued) MT90870 data sheet 40 zarlink semiconductor inc. figure 15 - backplane port external high impedance control timing (32 mb/s mode) 4.2.3 bors set high the backplane output enable bit ( be ) of the backplane connection memory has direct per-channel control on the high-impedance state of the backplane output streams, bsto0-31 (for non-32 mb/s mode) and bsto0-15 (for 32 mb/s mode). programming the be bit to a low state will set the stream output of the MT90870 to high impedance for the duration of the channel period. see sect ion 12.4, backplane connec tion memory bit definition, for programming details. the bcsto0-3 outputs remain active. bcsto0 bsto0 (32 mb/s) c8o fp8o ch 1 bsto0 ch 1 bsto4 ch 1 bsto8 ch 1 bsto12 ch 2 bsto0 ch 2 bsto4 ch 2 bsto8 ch 2 bsto12 ch 3 bsto0 ch 3 bsto4 ch 511 bsto8 ch 511 bsto12 ch 0 bsto0 ch 0 bsto4 ch 0 bsto8 ch 0 bsto12 ch 1 bsto0 ch 1 bsto4 ch 1 bsto8 ch 1 bsto12 ch 1 bsto1 ch 1 bsto5 ch 1 bsto9 ch 1 bsto13 ch 2 bsto1 ch 2 bsto5 ch 1 bsto9 ch 2 bsto13 ch 3 bsto1 ch 3 bsto5 ch 511 bsto9 ch 511 bsto13 ch 0 bsto1 ch 0 bsto5 ch 0 bsto9 ch 0 bsto13 ch 1 bsto1 ch 1 bsto5 ch 1 bsto9 ch 1 bsto13 ch 1 bsto2 ch 1 bsto6 ch 1 bsto10 ch 1 bsto14 ch 2 bsto2 ch 2 bsto6 ch 2 bsto10 ch 2 bsto14 ch 3 bsto2 ch 3 bsto6 ch 511 bsto10 ch 511 bsto14 ch 0 bsto2 ch 0 bsto6 ch 0 bsto10 ch 0 bsto14 ch 1 bsto2 ch 1 bsto6 ch 1 bsto10 ch 1 bsto14 ch 1 bsto3 ch 1 bsto7 ch 1 bsto11 ch 1 bsto15 ch 2 bsto3 ch 2 bsto7 ch 2 bsto11 ch 2 bsto15 ch 3 bsto3 ch 3 bsto7 ch 511 bsto11 ch 511 bsto15 ch 0 bsto3 ch 0 bsto7 ch 0 bsto11 ch 0 bsto15 ch 1 bsto3 ch 1 bsto7 ch 1 bsto11 ch 1 bsto15 bcsto1 bcsto2 bcsto3 one c16o cycle bsto1 (32 mb/s) bsto2 (32 mb/s) bsto3 (32 mb/s) channel 511 bits 7-0 channel 510 bits 7-0 channel 511 bits 7-0 channel 510 bits 7-0 channel 511 bits 7-0 channel 510 bits 7-0 channel 511 bits 7-0 channel 510 bits 7-0 channel 1 bits 7-0 channel 0 bits 7-0 channel 1 bits 7-0 channel 0 bits 7-0 channel 1 bits 7-0 channel 0 bits 7-0 channel 1 bits 7-0 channel 0 bits 7-0 MT90870 data sheet 41 zarlink semiconductor inc. 5.0 data delay through the switching paths for all data rates, the received serial data is convert ed to parallel format and stored sequentially in the data memory. each data memory location corresponds to an input stream and channel number. to provide constant delay and maintain frame integrity, the MT90870 utilizes four pages of data memory. consecutive frames are written in turn to each page of memory. reading is contro lled to allow a channel data written in frame n to be read during frame n+3. a constant delay of three frames is app lied to all switching paths irrespective of data-rate or channel number. see figure 16. figure 16 - constant switch delay: exampl es of different stream rates and routing ch 254 ch 0 ch 1 ch 254 ch 255 ch 254 ch 255 ch 0 ch 1 ch 0 ch 1 ch 255 bsti0 (16 mb/s) fp8o ch 254 ch 0 ch 1 ch 254 ch 255 ch 254 ch 255 ch 0 ch 1 ch 0 ch 1 ch 255 bsto1 (16 mb/s) frame n frame n+3 frame n+4 ch 0 ch 127 ch 127 ch 0 ch 0 ch 127 bsti0 (8 mb/s) ch 0 ch 127 ch 127 ch 0 ch 0 ch 127 lsto1 (8 mb/s) ch 0 ch 127 ch 127 ch 0 ch 0 ch 127 lsti0 (8 mb/s) ch 0 ch 63 ch 63 ch 0 ch 0 ch 63 bsto1 (4 mb/s) ch 0 ch 127 ch 127 ch 0 ch 0 ch 127 lsti0 (8 mb/s) ch 0 ch 31 ch 31 ch 0 ch 0 ch 31 lsto1 (2 mb/s) c h c h bsti0 (32 mb/s) ch 254 ch 0 ch 1 ch 254 ch 255 ch 254 ch 255 ch 0 ch 1 ch 0 ch 1 ch 255 lsto1 (16 mb/s) c h c h c h c h c h c h c h c h c h c h c h c h c h c h c h c h c h c h c h c h c h c h 511 0 example showing 32 mb/s mode, backplane to local switching example showing local to local switching example showing local to backplane switching example showing backplane to local switching example showing backplane to backplane switching frames n+1 and n+2 MT90870 data sheet 42 zarlink semiconductor inc. 6.0 connection memory description the MT90870 incorporates two connection memories, local connection memory and backplane connection memory. 6.1 local connection memory the local connection memory (lcm) is 16-bit wide with 4,096 memory locations to support the local output port. the most significant bit of each word, bit [15], selects the source stream from either t he backplane or the local port and determines the backplane-to- local or local-to-local data routing. bits [14:13] select the control modes of the local output streams, namely the per-channel message an d the per-channel high impedance output control modes. in connection mode (bit14 = low), bits [12:0] select t he source stream and channel number as detailed in table 5. in message mode (bit14 = high), bits [12:8] are unused and bits [7:0] contain the message byte to be transmitted. the control register bits ms2, ms1, and ms0 must be set to 000, respectively, to select the local connection memory for the write and read operatio ns via the microprocessor port. see section 7.0, microprocessor port, and section 13.1, control register (cr) for details on microprocessor port access. 6.2 backplane connection memory the backplane connection memory (bcm) is 16-bit wide wi th 8,192 memory locations to support the backplane output port. the most significant bit of each word, bit [1 5], selects the source stream from either the backplane or the local port and determines the local -to-backplane or backpl ane-to-backplane data routing. bits [14:13] select the control modes of the backplane output streams, namely the per-chann el message mode and the per-channel high impedance output control mode. in connection mode (bit 14 = low), bits [12:0] sele ct the source stream and channel number as detailed in table 5. in message mode (bit14 = high), bits [12:8] are unused and bits [7:0] contain the message byte to be transmitted. source stream bit rate source stream no. source channel no. 2 mb/s [12:8] legal values: 0 - 31 (backplane) 0 - 15 (local) [7:0] legal values 0 - 31 4 mb/s [12:8] legal values: 0 - 31 (backplane) 0 - 15 (local) [7:0] legal values 0 - 63 8 mb/s [12:8] legal values: 0 - 31 (backplane) 0 - 15 (local) [7:0] legal values 0 - 127 16 mb/s [12:8] legal values: 0 - 31 (backplane) 0 - 15 (local) [7:0] legal values 0 - 255 32 mb/s (backplane streams only) [12:9] legal values: 0 - 15 [8:0] legal values 0 - 511 table 5 - local and backplane connection memory configuration MT90870 data sheet 43 zarlink semiconductor inc. the control register bits ms2, ms1, and ms0 must be set to 001, respectively, to select the backplane connection memory for the write and read operatio ns via the microprocessor port. see section 7.0, microprocessor port, and section 13.1, control register (cr) for details on microprocessor port access. 6.3 connection memory block programming this feature allows fast, simultaneous, initialization of the local and backplane connection memories after power up. when the memory block programming mode is enabled, the contents of the bl ock programming register (bpr) will be loaded into the connection memories. see ta ble 16 and table 17 for details of the control register and block programming regist er values, respectively. 6.3.1 memory block programming procedure ? set the mbp bit in the control register from low to high. ? set the bpe bit to high in the block programming regist er (bpr). the local block programming data bits, lbpd2-0 , of the block programming register, will be loaded into bit 15, bit 14 and bit 13, respectively. of the local connection memory. the remaining bit positions are loaded with zeros as shown in table 6. table 6 - local connection memory in block programming mode the backplane block programming data bits, bbpd2-0 , of the block programming register, will be loaded into bit 15, bit 14 and bit 13, respectively, of the backplane connection memory. the remaining bit positions are loaded with zeros as shown in table 7. table 7 - backplane connection memory in block programming mode the block programming register bit, bpe will be automatica lly reset low within 125 us, to indicate completion of memory programming. the block programming mode can be te rminated at any time prior to completion by setting the bpe bit of the block programming register or the mbp bit of the control register to low. note the default values (low) of lbpd2-0 and bbpd2-0 of the block programming r egister, following a device reset, may be used. these settings shall set all output c hannels to high, or high-impedance , in accordance with the lors and bors pin conditions, see pin descri ption for further details. the local connection memory shall be configured to select data from channel 0 of backplane input stream 0 ( bsti0 ), and the backplane connection memory shall be configured to select data from channel 0 of local input stream 0 ( lsti0 ). alternative conditions may be established by programming bits lbpd2-0 and bbpd2-0 of the block programming register at the time of setting bit bpe to high. see section 12.3, local connection me mory bit definition, se ction 12.4, backplane connection memory bit definition, and sectio n 13.2, block program ming register (bpr). 7.0 microprocessor port the MT90870 supports non-multiplexed motorola micropro cessors. the microprocessor port consists of 16-bit parallel data bus ( d0-15 ), 15-bit address bus ( a0-14 ) and four control signals ( cs , ds , r/w and dta ). the data bus provides access to the internal registers, the backpl ane connection and data memories, and the local connection and data memories. each backplane memory has 8,192 locations and each local memory has 4,096 15 14 13 1211109876543210 lbpd2 lbpd1lbpd00000000000000 15 14 13 1211109876543210 bbpd2 bbpd1 bbpd0 0 000000000000 MT90870 data sheet 44 zarlink semiconductor inc. locations. see table 8, address map for data and c onnection memory locations (a14=1), for the address mapping. each connection memory can be read or written via the 16-bit microprocessor port. the data memories can only be read (but not written) fr om the microprocessor port. to prevent the bus ?hanging? in the ev ent of the MT90870 not receiving a mast er clock, the microprocessor port shall complete the dta handshake when accessed but any data read from the bus will be invalid. there must be a minimum of 30 ns between cpu access es, to allow the mt90869 device to recognize the accesses as separate (i.e. a minimum of 30 ns must separate the de-assertion of dta (to high) and the assertion of cs and/or ds to initiate the next access). 8.0 device power-up, initialization and reset 8.1 power-up sequence the recommended power-up sequence is for the vdd_io supply (nominally +3.3 v) to be established before the power-up of the vdd_pll and vdd_core supplies (nominally +1.8 v). the vdd_pll and vdd_core supplies may be powered up simultaneously, but neither shoul d 'lead' the vdd_io supply by more than 0.3 v. all supplies may be powered-down simultaneously. 8.2 initialization upon power up, the MT90870 should be initia lized by applying the following sequence: 8.3 reset the reset pin is used to reset the device. when set low, an asynchronous reset is applied to the MT90870. it is synchronized to the internal clock and remains active for 50 us following release (set high) of the external reset to allow time for the pll to fully settle. during the reset period, depending on the state of input pins lors and bors , the output streams lsto0-15 and bsto0-31 are set to high or high impedance, and all internal registers and count ers are reset to the default state. the reset pin must remain low for two input clock cycles (c8i) to guarantee a synchronized reset release. 1 ensure the trst pin is permanently low to disable the jtag tap controller. 2set ode pin to low. this configures the lcsto0-1 output signals to low (i.e., to set optional external output buffers to high impedance), and sets the lsto0-15 outputs to high or high impedance, dependent on the lors input value, and sets the bcsto0-3 output signals to low (i.e., to set optional external output buffers to high impedance), and sets the bsto0-31 outputs to high or high impedance, dependent on bors input value. refer to pin description for details of the lors and bors pins. 3 reset the device by pulsing the reset pin to zero for at least two cycles of the input clock, c8i . 4 use the block programming mode to initia lize the local and the backplane connection memories. refer to section 6.3, connection memory block programming. 5set ode pin to high after the connection memories are programmed to ensure that bus contention will not occur at the serial stream outputs. MT90870 data sheet 45 zarlink semiconductor inc. when a reset is applied to the MT90870, the cs line is inhibited and the dta line may become active through simultaneous microport activity. external gating of the dta line with cs is recommended to avoid bus conflict in applications incorporating multiple dev ices with individual reset conditions. 9.0 bit error rate test independent bit error rate (ber) test mechanisms are pr ovided for the local and backplane ports. in both ports there is a ber transmitter and a ber receiver. the transmitter and receiver are each independently controlled to allow either looped back, or uni-directional testing. the transmitter generates a 2 15 -1 or 2 23 -1 pseudo random binary sequence (prbs), which may be allocated to a specific stream and a number of cha nnels. this is defined by a stream number, a start channel number, and the num ber of consecutive channels following the start channel. the stream, channel number and the number of consecutiv e channels following the start channel are similarly allocated for the receiver and detection of the prbs. exam ples of a channel sequence are presented in figure 17. when enabled, the receiver attempts to lock to the pr bs on the incoming bit stream. once lock is achieved, by detection of a seed value, a bit by bit comparison takes place and each error shall increment a 16-bit counter. a counter ?roll-over? shall occur in the even t of an error count in excess of 65535. the ber operations are controll ed by registers as follows (refer to section 13.3, bi t error rate test control register (bercr) for overall control, section 13.10, local bit error rate (ber) registers and section 13.11, backplane bit error rate (ber) regist ers for register pr ogramming details): ? ber control register ( bercr ) - independently enables ber transmission and receive testing for backplane and local ports. ? local and backplane ber start send registers ( lbssr and bbssr ) - defines the output stream and start channel for ber transmission. ? local and backplane transmit ber length registers ( ltxblr and btxblr ) - defines, for transmit stream, how many consecutive channels to follow the start channel. ? local and backplane ber start receive registers ( lbsr and bbsr ) - define the input stream and channel from where the ber sequence will start to be compared. ? local and backplane receive ber length registers ( lrxblr and brxblr ) - defines, for the receive stream, how many consecutive channels follow the start channel. ? local and backplane ber count registers ( lbcr and bbcr ) - contain the number of counted errors. the registers listed completely define the transmit stream and channels. when ber transmission is enabled for these channels, the source bits and the message mode bits, lsrc and lmm in the local connection memory, and bsrc and bmm in the backplane connection memory , are ignored. the enable bits ( le and be ) of the respective connection memories should be set to high to enable the outputs for the selected channels. MT90870 data sheet 46 zarlink semiconductor inc. figure 17 - examples of ber transmission channels 10.0 memory built-in-self-test (bist) mode as operation of the memory bist will corrupt existing data, this test must only be performed when the device is placed ?out-of-service? or isolated from live traffic. the memory bist mode is enabled through the microproce ssor port (section 13.14, memory bist register). internal bist memory controllers generate the memory test pattern (s-march) and control the memory test. the memory test result is monitored through the memory bist register when contro lled via the microprocessor interface. 11.0 jtag port the MT90870 jtag interface conforms to the boundary- scan ieee 1149.1 standard. the operation of the boundary-scan circuit shall be controlled by an external test access port (tap) controller. jtag is intended to be used during the development cycle. the jtag in terface is operational when the MT90870 core (v dd _core) is powered at typical voltage levels. 11.1 test access port (tap) the test access port (tap) consists of four in put pins and one output pin described as follows: ? test clock input (tck) tck provides the clock for the tap controller and is independent of any on-chip clock. tck permits the shifting of test data into or out of the boundar y-scan registers cells, under the control of the tap controller in boundary-scan mode. ? test mode select input (tms) the tap controller uses the logic signals applied to the tms input to control test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin in in ternally pulled to v dd_io when not driven from an external source. frame boundary 0 1 2 ...... ..... 254 3 ..... ..... 255 0 1 2 ...... ..... 254 3 ..... ..... 255 0 1 2 ...... ..... 254 3 ..... ..... 255 0 1 channels containing data (traffic) channels containing prbs sequence start ch=0 length=256 start ch=0 length=3 start ch=254 length=4 0 0 1 1 fp8i fp stream once started ber transmission continues until stopped by the ber control register: 2 2 2 note: length = start chan. + no. of consecutive channels MT90870 data sheet 47 zarlink semiconductor inc. ? test data input (tdi) depending on the previously applied data to the tms input, the serial input data applied to the tdi port is connected either to the instructio n register or to a test data regist er. both registers are described in a section 11.2, tap registers. the applied input data is sampled at the rising edge of tck pulses. this pin is internally pulled to v dd_io when not driven from an external source. ? test data output (tdo) depending on the previously applied sequence to the tms input, the contents of either the instruction register or data register are se rially shifted out towards the tdo . the data out of the tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo output is set to a high impedance state. ? test reset (trst ) trst provides an asynchronous reset to the jtag scan structure. this pin is internally pulled to v dd_io when not driven from an external source. 11.2 tap registers the MT90870 uses the public instructions defined in the ie ee 1149.1 standard with the provision of an instruction register and three test data registers. 11.2.1 test instruction register the jtag interface contains a four-bit instruction regist er. instructions are serially loaded into the instruction register from the tdi pin when the tap controller is in the shift-ir state. instructions are subsequently decoded to achieve two basic functions: to select the test data regi ster to operate while the inst ruction is current, and to define the serial test data regi ster path to shift data between tdi and tdo during data register scanning. 11.2.2 test data registers 11.2.2.1 the bo undary-scan register the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the MT90870 core logic. 11.2.2.2 the bypass register the bypass register is a single stage shift register to provide a one-bit path from tdi to tdo . 11.2.2.3 the device identification register the jtag device id for the MT90870 is 0087014b h . version, bits <31:28>: 0000 part no., bits <27:12>: 0000 1000 0111 0000 manufacturer id, bits <11:1>: 0001 0100 101 header, bit <0> (lsb): 1 11.3 boundary scan description language (bsdl) file a boundary scan description language (bsdl) file is availabl e from zarlink semiconductor to aid in the use of the ieee 1149.1 test interface. MT90870 data sheet 48 zarlink semiconductor inc. 12.0 memory address mappings the device contains two data memory blocks, one for received backplane data and one for received local data. for all data rates the received data is converted to parallel form at by internal serial to parallel converters and stored sequentially in the relevant data memory. 12.1 backplane data memory bit definition the 8-bit backplane data memory (bdm) has 8,192 positions. the locations are associated with the backplane input streams and channels. the address bits (a13:0) of the mi croprocessor define the ad dresses of the streams and the channels. the bdm is configured as follows: 12.2 local data memory bit definition the 8-bit local data memory (ldm) has 4,096 positions. th e locations are associated wi th the local input streams and channels. the address bits of the microprocessor de fine the addresses of the streams and the channels. the ldm is configured as follows: table 10 - local data memory (ldm) bits address bit description a14 selects memory or register access a13-a9 stream address (0-31) a8-a0 channel address (0-511) notes: 1. bit a14 must be high for accessing to data and connection memory positions. bit a14 must be low for accessing registers. 2. streams 0 to 15 are used when the back plane serial streams are at 32.768 mb/s. 3. channels 0 to 31 are used when serial stream is at 2.048 mb/s. 4. channels 0 to 63 are used when serial stream is at 4.096 mb/s. 5. channels 0 to 127 are used when serial stream is at 8.192 mb/s. 6. channels 0 to 255 are used when serial stream is at 16.384 mb/s. 7. channels 0 to 511 are used when serial stream is at 32.768 mb/s. table 8 - address map for data and connection memory locations (a14=1) bit name description 15-8 reserved set to a default value of 0 7-0 bdm backplane data memory backplane input channel data table 9 - backplane data memory (bdm) bits bit name description 15-8 reserved set to a default value of 0 7-0 ldm local data memory local input channel data MT90870 data sheet 49 zarlink semiconductor inc. 12.3 local connection memory bit definition the local connection memory (lcm) has 4,096 addresses of 16-bit words. each address, accessed through bits a13-a0 of the microprocessor port, is allocated to an individual local output stream and channel. the bit definition for each 16-bit word is presented in table 11 for loc al-to-local and backplane (non-32 mb/s mode)-to-local connections, and in table 12, for loc al-to-local and backplane(32 mb/s mode)-to-local connections. bit lsrc selects the switch configuration fo r backplane-to-local or local-to-local . when the per-channel message mode is selected (lmm = high), the lower byte of the lcm wo rd (lcab7-0) will be transmitted as data on the output stream (lsto0-15) in place of data defined by the source control, stream and channel address bits. . bit name description 15 lsrc source control bit when low, the source is from the ba ckplane input port (backplane data memory). when high, the source is from the local input port (local data memory). ignored when lmm is set high. 14 lmm local message mode bit when low, the channel is in connection mode. when high, the channel is in message mode. 13 le local output enable bit when low the channel may be high impedance, ei ther at the device output, or set by an external buffer dependent upon the lors pi n. when high the channel is active. 12-8 lsab4-0 source stream address bits the binary value of these 5 bits re presents the input stream number. ignored when lmm is set high. 7-0 lcab7-0 source channel address bits the binary value of these 8 bits represents the input channel number when lmm is set low. transmitted as data when lmm is set high. table 11 - lcm bits for local-to-local and b ackplane (non-32 mb/s mode)-to-local switching bit name description 15 lsrc source control bit. when low, the source is from the ba ckplane input port (backplane data memory). when high, the source is from the local input port (local data memory). ignored when lmm is set high. 14 lmm local message mode bit when low, the channel is in connection mode. when high, the channel is in message mode. 13 le local output enable bit when low, the channel may be high impedance, either at the device output or set by an external buffer, dependent upon the lors pin. when high, the channel is active. 12-9 lsab3-0 source stream address bits. the binary value of these 4 bits re presents the input stream number. ignored when lmm is set high. 8-0 lcab8-0 channel address bits. the binary value of these 9 bits represents the input channel number, when lmm is low. bits lcab7-0 transmitted as data when lmm is set high. table 12 - lcm bits for backplane( 32 mb/s mode)-to-local switching MT90870 data sheet 50 zarlink semiconductor inc. 12.4 backplane connec tion memory bit definition the backplane connection memory (bcm) has 8,192 addresse s of 16-bit words. each address, accessed through bits a13-a0 of the microprocessor port, is allocated to an individual backplane output stream and channel. the bit definition for each 16-bit word is presented in ta ble 13 for local-to- backplane (non-32 mb/s mode) and backplane-to-backplane (non-32 mb/s mode) connecti ons, and in table 14, for local-to-backplane (32 mb/s mode) and backplane-to-backplane (32 mb/s mode) connections. bit bsrc selects the switch configuration for local-t o-backplane or backplane-to-backplane. when the per- channel message mode is select ed (bmm = high), the lower byte of t he bcm word (bcab7-0) will be transmitted as data on the output stream (bsto0-31) in place of dat a defined by the source control, stream address and channel address bits. bit name description 15 bsrc backplane source control bit. when low, the source is from the local input port (local data memory). when high, the source is from the backplane input port (backplane data memory). ignored when bmm is set high. 14 bmm backplane message mode bit. when low, the channel is in connection mode . when high, the channel is in message mode. 13 be backplane output enable bit. when low the channel may be high impedance, ei ther at the device output or set by an external buffer, dependent upon the bors pi n. when high the channel is active. 12-8 bsab4-0 backplane source stream address bits. the binary value of these 5 bits represents the input stream number. bsab4-0 are ignored when bmm is set high in message mode. 7-0 bcab7-0 source channel address bits. the binary value of these 8 bits represents the input channel number when bmm is set low. bcab7-0 are transmitted as data when bmm is set high in message mode. table 13 - bcm bits for local-to-backplane and backplane-to-backplane switching (non-32 mb/s mode) bit name description 15 bsrc backplane source control bit. when low, the source is from the local input port (local data memory). when high, the source is from the backplane input port (backplane data memory). bsrc is ignored when bmm is set high in message mode. 14 bmm backplane message mode bit. when low, the channel is in connection mode. when high, the channel is in message mode. 13 be backplane output enable bit. when this bit is low the channel may be high im pedance, either at the device output or set by an external buffer, dependent upon the bors pin. when the bit is high the channel is active. 12-9 bsab3-0 backplane source stream address bits. the binary value of these 4 bits represents the input stream number. bsab3-0 are ignored when bmm is set high in message mode. MT90870 data sheet 51 zarlink semiconductor inc. table 14 - bcm bits for backplane-to-backplane switching (32 mb/s mode) 12.5 internal register mappings 8-0 bcab8-0 source channel address bits. the binary value of these 9 bits represents the input channel number, when bmm is low. bits bcab7-0 transmitted as data when bmm is set high in message mode. a14 - a0 register 0000 h control register, cr 0001 h block programming register, bpr 0002 h ber control register, bercr 0003 h - 0012 h local input channel delay register 0, lcdr0 - register 15, lcdr15 0023 h - 0032 h local input bit delay register 0, lidr0 - register 15, lidr15 0043 h - 0062 h backplane input channel delay regist er 0, bcdr0 - register 31, bcdr31 0063 h - 0082 h backplane input bit delay register 0, bidr0 - register 31, bidr31 0083 h - 0092 h local output advancement register 0, loar0 - register 15, loar15 00a3 h - 00c2 h backplane output advancement regist er 0, boar0 - register 31, boar31 00c3 h local ber start send register, lbssr 00c4 h local transmit ber length register, ltxblr 00c5 h local receive ber length register, lrxblr 00c6 h local ber start receive register, lbsrr 00c7 h local ber count register, lbcr 00c8 h backplane ber start send register, bbssr 00c9 h backplane transmit ber length register, btxblr 00ca h backplane receive ber length register, brxblr 00cb h backplane ber start receive register, bbsrr 00cc h backplane ber count register, bbcr 00cd h - 00dc h local input bit rate register 0, librr0 - register 15, librr15 00ed h - 00fc h local output bit rate register 0, lobrr0 - register 15, lobrr15 010d h - 012c h backplane input bit rate register 0, bibrr0 - register 31, bibrr31 012d h - 014c h backplane output bit rate register 0, bobrr0 - register 31, bobrr31 014d h memory bist register, mbistr 3fff h revision control register, rcr table 15 - address map for register (a14 = 0) bit name description MT90870 data sheet 52 zarlink semiconductor inc. 13.0 detailed register description this section describes the regist ers that are used in the device. 13.1 control register (cr) address 0000h. the control register defines which memory is to be acce ssed. it initiates the memory block programming mode and selects the backplane data rate mode. the control register ( cr ) is configured as follows: bit name reset description 15-9 reserved 0 reserved . 8fpw 0 frame pulse width when low, an input frame pulse width of 122 ns shall be applied to fp8i . when high, an input frame pulse width of 244 ns shall be applied to fp8i . 7 mode32 0 32 mhz mode when low, backplane streams (bsti0-31 and bsto0-31) may be individually programmed for data-rates of 2, 4, 8, or 16 mb/s. when high, the backplane streams (bsti0-15 and bsto0-15) operate in 32mb/s mode. 6c8ipol 0 8 mhz input clock polarity the input frame boundary must be aligned to the c8i clock rising edge. this bit, c8ipol, must be set high to achieve correct frame boundary alignment. if this bit is low, the input frame boundary alignment will not work correctly. 5 copol 0 output clock polarity when set low, the output clock is the same polarity as the input clock. when set high, the output clock is inverted. this applies to both 8 mhz (c8o )and 16 mhz (c16o ) output clocks. 4mbp 0 memory block programming when low, the memory block programmi ng mode is disabled. when high, the connection memory block programming mode is ready to program the local connection memory (lcm), and the backplane connection memory (bcm). 3osb 0 output stand by this bit enables the bsto0 - 31 and the lsto0 - 15 serial outputs . when set low, the bsto0-31 and lsto0-15 are driven high or high impedance, dependent on the bors and lors pin settings respectively, and bcsto0-3 and lcsto0-1 are driven low. when set high, the bsto0-31, lsto0- 15, bcsto0-3 and lcsto0-1 are enabled. table 16 - control register bits output control with ode pin and osb bit ode pin osb bit bsto0 - 31, lsto0 - 15 0 x disable 1 0 disable 1 1 enable MT90870 data sheet 53 zarlink semiconductor inc. figure 18 - frame boundary conditions, st- bus operation 2-0 ms(2:0) 0 memory select bits. these three bits select the connection or data memory for subsequent micro-port memory access operations: 000, local connection memory (lcm) is selected for read or write operations. 001, backplane connection memory (bcm) is selected for read or write operations. 010, local data memory is selected for read-only operation. 011, backplane data memory is selected for read-only operation. bit name reset description table 16 - control register bits (continued) frame boundary c8i fp8i frame pulse width = 122 ns, control register bit8 (fpw) = 0 control register bit6 (c8ipol) = 1 (a) frame pulse width = 244 ns, control register bit8 (fpw) = 1 control register bit6 (c8ipol) = 1 (b) c8i fp8i MT90870 data sheet 54 zarlink semiconductor inc. figure 19 - frame boundary conditions, gci - bus operation 13.2 block prog ramming register (bpr) address 0001h. the block programming register stores the bit pattern s to be loaded into the connection memories when the memory block programming feature is enabled. the bpe, lbpd2-0 and bbpd2-0 bits in the bpr register must be defined in the same write operation. the bpe bit is set high, to commence the block programming operation. pr ogramming is completed in one frame period and may be instigated at any ti me within a frame.the bpe bit return s to low to indicate the block programming functi on has completed. when bpe is high, no other bits of t he bpr register must be changed for at least a single frame period, except to abort the programming operation. the pr ogramming operation may be aborted by se tting either bpe to low, or the control register bit, mbp, to low. the bpr register is configured as follows. . frame boundary pulse width = 122 ns, control register bit8 (fpw) = 0 control register bit6 (c8ipol) = 1 (a) pulse width = 244 ns, control register b it8 (fpw) = 1 control register bit6 (c8ipol) = 1 (b) c8i fp8i c8i fp8i MT90870 data sheet 55 zarlink semiconductor inc. 13.3 bit error rate test control register (bercr) address 0002h. the ber control register controls backplane and loca l port ber testing. it independently enables and disables transmission and reception. it is configured as follows: bit name reset description 15-7 unused 0 set low. 6-4 bbpd(2:0) 0 backplane block programming data. these bits refer to the value loaded into the backplane connection memory (bcm) when the memory block programming feature is activated. when the mbp bit in the control register (cr) is set high and the bpe is set high, the contents of bits bbpd2-0 are loaded into bits 15-13, respectively, of the bcm. bits 12-0 of the bcm are set low. 3-1 lbpd(2:0) 0 local block programming data. these bits refer to the value loaded in to the local connection memory (lcm), when the memory block programming featur e is activated. when the mbp bit in the control register is set high and t he bpe is set high, the contents of bits lbpd2-0 are loaded into bits 15- 13, respectively, of the lcm. bits 12-0 of the lcm are set low. 0 bpe 0 block programming enable. a low to high transition of this bi t enables the memory block programming function. a low will be returned afte r 125 us, upon completion of programming. set low to abort the programming operation. table 17 - block programming register bits bit name reset description 15-12 reserved 0 reserved. 11 lockb 0 backplane lock (read only). this bit is automatically set high when the receiver has locked to the incoming data sequence. the bit is reset by a low to high transition on sberrxb. 10 prstb 0 pber reset for backplane. a low to high transition initializes the backplane ber generator to the seed value. 9 cberb 0 clear bit error rate register for backplane. a low to high transition in this bit resets the backplane internal bit error counter and the backplane bit erro r (bberr) register to zero. table 18 - bit error rate test control register (bercr) bits MT90870 data sheet 56 zarlink semiconductor inc. 8 sberrxb 0 start bit error rate receiver for backplane. a low to high transition enables the backplane ber receiver. the receiver monitors incoming data for reception of the seed value. when detected, the lock state is indicated (lockb) and the receiver compares the incoming bits with the reference generator for bit equality and increments the backplane bit error register (bbcr) on each failure. when set low, bit comparison is disabled and the error count is frozen. the error count is stored in the backplane bit error register (bbcr). 7 sbertxb 0 start bit error rate tr ansmitter for backplane. a low to high transition starts the ber transmission. when set low, transmission is disabled. 6prbsb 0 ber mode select for backplane. when set high, a prbs sequence of length 2 23 -1 is selected for the backplane port. when set low, a prbs sequence of length 2 15 -1 is selected for the backplane port. 5lockl 0 local lock (read only). this bit is automatically set high when the receiver has locked to the incoming data sequence. the bit is reset by a low to high transition on sberrxl 4prstl 0 pber reset for local. a low to high transition initializes the local ber generator to the seed value. 3 cberl 0 clear bit error rate register for local. a low to high transition resets the local internal bit error counter and the local bit error (lberr) register to zero. 2 sberrxl 0 start bit error rate receiver for local. a low to high transition enables t he local ber receiver. the receiver monitors incoming data for reception of the seed value. when detected, the lock state is indicated (lockl) and the receiver compares the incoming bits with the reference generator for bi t equality and increments the local bit error register (lbcr) on each failure. when set low, bit comparison is disabled and the error count is frozen. the error count is stored in the local bit error register (lbcr). 1 sbertxl 0 start bit error rate transmitter for local. a low to high transition enables the local ber transmission. when set low, transmission is disabled. 0prbsl 0 ber mode select for local. when set high, a prbs sequence of length 2 23 -1 is selected for the local port. when set low, a prbs sequence of length 2 15 -1 is selected for the local port. bit name reset description table 18 - bit error rate test control register (bercr) bits (continued) MT90870 data sheet 57 zarlink semiconductor inc. 13.4 local input channel delay registers (lcdr0 to lcdr15) address 0003h to 0012h. sixteen local input channel delay regist ers (lcdr0 to lcdr15) allow users to program the input channel delay for the local input data streams lsti0-15. th e possible adjustment is 255 channels and the lcdr0 to lcdr15 registers are conf igured as follows: : 13.4.1 local channel delay bits 7-0 (lcd7 - lcd0) these eight bits define the delay, in channel numbers, the serial interface re ceiver takes to store the channel data from the local stream input pins. the input channel delay can be set to 255 (16 mb/s streams), 127 (8 mb/s streams), 63 (4 mb/s streams) or 31 (2 mb/s streams) from the frame boundary. lcdrn bit (where n = 0 to 15) name reset description 15-8 reserved 0 reserved 7-0 lcd(7:0) 0 local channel delay register the binary value of these bits refers to the channel delay value for the local input stream. table 19 - local channel delay register (lcdrn) bits input stream channel delay corresponding delay bits lcd7-lcd0 0 channel (default) 0000 0000 1 channel 0000 0001 2 channels 0000 0010 3 channels 0000 0011 4 channels 0000 0100 5 channels 0000 0101 ... ... ... ... 253 channels 1111 1101 254 channels 1111 1110 255 channels 1111 1111 table 20 - local input channel delay programming table MT90870 data sheet 58 zarlink semiconductor inc. 13.5 local input bit delay registers (lidr0 to lidr15) address 0023h to 0032h. sixteen local input delay registers (lidr0 to lidr15) allo w users to program the input bit delay for the local input data streams lsti0-15. the possible adjustment is up to 7 3/ 4 of the data rate, advancing forward with a resolution of 1/4 of the data rate. the data rate can be either 2 mb/s, 4 mb/s, 8 mb/s or 16 mb/s. the lidr0 to lidr15 registers are conf igured as follows: 13.5.1 local input delay bits 4-0 (lid4 - lid0) these five bits define the delay from the bit boundary that the rece iver uses to sample each input. input bit delay adjustment can range up to 7 3 / 4 bit periods forward, with resolution of 1 / 4 bit period. this can be described as: lidn(4:0) = (no. of bits delay) / 4 for example, if lidn(4:0) is set to 10011 (19), the input bit delay = 19 * 1 / 4 = 4 3 / 4. table 22, local input bit delay programming table, illustrates the bit delay selection. lidrn bit (where n = 0 to 15) name reset description 15-5 reserved 0 reserved 4-0 lidn(4:0) 0 local input bit delay register the binary value of these bits refers to the input bit delay value for the local input stream table 21 - local channel delay register (lidrn) bits corresponding delay bits data rate lid4 lid3 lid2 lid1 lid0 0 (default) 00000 1/4 00001 1/2 00010 3/4 00011 1 00100 1 1/4 00101 1 1/2 00110 1 3/4 00111 2 01000 2 1/4 01001 2 1/2 01010 2 3/4 01011 3 01100 3 1/4 01101 3 1/2 01110 3 3/4 01111 table 22 - local input bit delay programming table MT90870 data sheet 59 zarlink semiconductor inc. 13.6 backplane in put channel delay regist ers (bcdr0 to bcdr31) address 0043h to 0062h thirty-two backplane input channel delay registers (bcdr 0 to bcdr31) allow users to program the input channel delay for the backplane input data streams bsti0- 31. the possible adjustment is 511 channels and the bcdr0 to bcdr31 registers are configured as follows: 13.6.1 backplane channel delay bits 8-0 (bcdn8 - bcdn0) these nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data from the backplane stream input pins. the input channel delay can be set to 511 (32 mb/s streams), 255 (16 mb/s streams), 127 (8 mb/s streams), 63 (4 mb/s stream s) or 31 (2 mb/s streams) from the frame boundary. 4 10000 4 1/4 10001 4 1/2 10010 4 3/4 10011 5 10100 5 1/4 10101 5 1/2 10110 5 3/4 10111 6 11000 6 1/4 11001 6 1/2 11010 6 3/4 11011 7 11100 7 1/4 11101 7 1/2 11110 7 3/4 11111 bcdrn bit (where n = 0 to 31 for non-32mb/s mode, n = 0 to 15 for 32mb/s mode) name reset description 15-9 reserved 0 reserved 8-0 bcd(8:0) 0 backplane channel delay register the binary value of these bits refers to the channel delay value for the backplane input stream table 23 - backplane channel delay register (bcdrn) bits corresponding delay bits data rate lid4 lid3 lid2 lid1 lid0 table 22 - local input bit delay programming table (continued) MT90870 data sheet 60 zarlink semiconductor inc. 13.7 backplane input bit delay registers (bidr0 to bidr31) address 0063h to 0082h thirty-two backplane input delay regist ers (bidr0 to bidr31) allow users to program the input bit delay for the backplane input data streams bsti0-31. the possible adjustm ent is 7 3/4 of the data rate, in steps of 1/4 of the data rate. the data rate can be either 2 mb/s, 4 mb/s, 8 mb/s, 16 mb/s, or 32 mb/s. the bidr0 to bidr31 registers are conf igured as follows: 13.7.1 backplane input delay bits 4-0 (bid4 - bid0) these five bits define how long in the cycle the serial in terface receiver takes to recognize and stores the bit 0 from the bsti input pins: i.e., start assuming a new fr ame. input bit delay adjustment can range up to 7 3 / 4 bit periods forward with resolution of 1 / 4 bit period. this can be described as bidn(4:0) = (no. of bits delay) / 4 for example, if bid(4:0) is set to 10011 (19), the input bit delay = 19 * 1 / 4 = 4 3 / 4. input stream channel delay corresponding delay bits bcd8-bcd0 0 channel (default) 0 0000 0000 1 channel 0 0000 0001 2 channels 0 0000 0010 3 channels 0 0000 0011 4 channels 0 0000 0100 5 channels 0 0000 0101 ... ... ... ... 509 channels 1 1111 1101 510 channels 1 1111 1110 511 channels 1 1111 1111 table 24 - backplane input channel delay (bcd) programming table bidrn bit (where n = 0 to 31 for non-32mb/s mode, n = 0 to15 for 32mb/s mode) name reset description 15-5 reserved 0 reserved 4-0 bid(4:0) 0 backplane input bit delay register the binary value of these bits refers to the input bit delay value for the backplane input stream table 25 - backplane input bit delay register (bidrn) bits MT90870 data sheet 61 zarlink semiconductor inc. table 26 illustrates the bit delay selection. 13.8 local output advancement registers (loar0 to loar15) address 0083h to 0092h. sixteen local output advancement regi sters (loar0 to loar15) allow users to program the output advancement for output data streams lsto0 to lsto15. the possible adjustm ent is -2, -4 or -6 cycles of the internal system clock (131.072 mhz). corresponding delay bits data rate bid4 bid3 bid2 bid1 bid0 0 (default) 00000 1/4 00001 1/2 00010 3/4 00011 1 00100 1 1/4 00101 1 1/2 00110 1 3/4 00111 2 01000 2 1/4 01001 2 1/2 01010 2 3/4 01011 3 01100 3 1/4 01101 3 1/2 01110 3 3/4 01111 4 10000 4 1/4 10001 4 1/2 10010 4 3/4 10011 5 10100 5 1/4 10101 5 1/2 10110 5 3/4 10111 6 11000 6 1/4 11001 6 1/2 11010 6 3/4 11011 7 11100 7 1/4 11101 7 1/2 11110 7 3/4 11111 table 26 - backplane input bit delay programming table MT90870 data sheet 62 zarlink semiconductor inc. the loar0 to loar15 registers are conf igured as follows: 13.8.1 local output advancement bits 1-0 (loa1-loa0) the binary value of these two bits is the amount of offset that a particul ar stream output can be advanced. when the advancement is 0, the serial output stream has the normal ali gnment with the local frame pulse. 13.9 backplane output advancement registers (boar0 - 31) address 00a3h to 00c2h thirty-two backplane output advancement registers (boar0 to boar3) allow users to program the output advancement for output data streams bsto0 to bsto31. for 2 mb/s, 4 mb/s, 8 mb/s and 16 mb/s stream operation the possible adjustment is -2, -4 or -6 cycles of t he internal system clock ( 131.072mhz). for 32 mb/ s stream operation the possible adjustment is -1, -2 or -3 c ycles of the internal syst em clock (131.072 mhz). the boar0 to boar3 registers are configured as follows: 13.9.1 backplane output advancement bits 1-0 (boa1-boa0) the binary value of these two bits is the amount of offset that a particul ar stream output can be advanced. when the advancement is 0, the serial out put stream has the normal alignmen t with the backplane frame pulse. loarn bit (where n = 0 to 15) name reset description 15-2 reserved 0 reserved 1-0 loa(1:0) 0 local output advancement register table 27 - local output advancement register (loarn) bits local output advancement corresponding advancement bits clock rate 131.072 mhz loa1 loa0 0 (default) 0 0 -2 cycle 0 1 -4 cycles 1 0 -6 cycles 1 1 table 28 - local output advancement (loar) programming table boarn bit (where n = 0 to 31 for non-32 mb/s mode, n = 0 to 15 for 32 mb/s mode) name reset description 15-2 reserved 0 reserved 1:0 boa(1:0) 0 backplane output advancement register table 29 - backplane output advancement register (boar) bits MT90870 data sheet 63 zarlink semiconductor inc. 13.10 local bit error rate (ber) registers 13.10.1 local ber start send register (lbssr) address 00c3h. local ber start send register defines the output channel and the stream in which the ber sequence starts to be transmitted. the lbssr register is configured as follows: 13.10.2 local transmit ber length register (ltxblr) address 00c4h local ber transmit length register ( ltxblr ) defines how many channels the ber seq uence will be transmitted during each frame. the ltxblr register is configured as follows: backplane output advancement for 2 mb/s, 4 mb/s, 8 mb/s & 16 mb/s backplane output advancement for 32 mb/s corresponding advancement bits clock rate 131.072 mhz clock rate 131.072 mhz boa1 boa0 0 (default) 0 (default) 0 0 -2 cycle -1 cycle 0 1 -4 cycles -2 cycle 1 0 -6 cycles -3 cycle 1 1 table 30 - backplane output advancement (boar) programming table bit name reset description 15-12 reserved 0 reserved. 11-8 lbssa(3:0) 0 local ber send stream address bits. the binary value of these bits refers to the local output stream which carries the ber data. 7-0 lbsca(7:0) 0 local ber send channel address bits. the binary value of these bits refe rs to the local output channel in which the ber data starts to be sent. table 31 - local ber start send register (lbssr) bits bit name reset description 15-8 reserved 0 reserved . table 32 - local transmit ber length register (ltxblr) bits MT90870 data sheet 64 zarlink semiconductor inc. 13.10.3 local receive ber length register (lrxblr) address 00c5h local ber receive length register ( lrxblr ) defines how many channels t he ber sequence will be received during each frame. the lrxblr register is configured as follows: 13.10.4 local ber start receive register (lbsrr) address 00c6h local ber start receive register def ines the input stream and start chann el and the stream in which the ber sequence shall be received. the lbsrr register is configured as follows: 7-0 ltxbl(7:0) 0 local transmit ber length bits the binary value of these bits define t he number of channels in addition to the start channel that the ber data will be transmitted on. (i.e. total channels = start channel + ltxbl value) bit name reset description 15-8 reserved 0 reserved . 7-0 lrxbl(7:0) 0 local receive ber length bits the binary value of these bits define the number of channels in addition to the start channel allocated for the ber receiver. (i.e. total channels = start channel + lrxbl value) table 33 - local receive ber length register (lrxblr) bits bit name reset description 15-12 reserved 0 reserved. 11-8 lbrsa(3:0) 0 local ber receive stream address bits the binary value of these bits refers to the local input stream to receive the ber data. 7-0 lbrca(7:0) 0 local ber receive channel address bits the binary value of these bits refers to the local input channel in which the ber data starts to be compared. table 34 - local ber start receive register (lbsrr) bits bit name reset description table 32 - local transmit ber length register (ltxblr) bits MT90870 data sheet 65 zarlink semiconductor inc. 13.10.5 local ber count register (lbcr) address 00c7h local ber count register contains the number of counted errors. this register is read only. the lbcr register is configured as follows: 13.11 backplane bit error rate (ber) registers 13.11.1 backplane ber start send register (bbssr) address 00c8h backplane ber start send register defines the output channel and the stream in which the ber sequence is transmitted. the bbssr register is configured as follows: 13.11.2 backplane transmit ber length register (btxblr) address 00c9h backplane transmit ber length register ( btxblr ) defines how many channels in each frame the ber sequence will be transmitted. the btxblr register is configured as follows: bit name reset description 15-0 lbc(15:0) 0 local bit error rate count the binary value of the bits de fine the local bit error count. table 35 - local ber count register (lbcr) bits bit name reset description 15-14 reserved 0 reserved. 13-9 bbssa(4:0) 0 backplane ber send stream address bits the binary value of these bits de fine the backplane output stream to transmit the ber data. 8-0 bbsca(8:0) 0 backplane ber send channel address bits the binary value of these bits define the backplane output start channel in which the ber data is transmitted. table 36 - backplane ber start send register (bbssr) bits bit name reset description 15-9 reserved 0 reserved. 8-0 btxbl(8:0) 0 backplane transmit ber length bits the binary value of these bits define t he number of channels in addition to the start channel allocated for the ber tran smitter. (i.e. total channels = start channel + btxbl value) table 37 - backplane transmit ber length (btxblr) bits MT90870 data sheet 66 zarlink semiconductor inc. 13.11.3 backplane receive ber length register (brxblr) address 00cah backplane receive ber length register ( brxblr ) defines how many channels in each frame the ber sequence will be transmitted. the brxblr register is configured as follows: 13.11.4 backplane ber start receive register (bbsrr) address 00cbh backplane ber start receive register defines the inpu t stream and the start channel in which the ber sequence shall be received. the bbsrr register is configured as follows: 13.11.5 backplane be r count register (bbcr) address 00cch backplane ber count register contains the number of counted errors. this register is read only. the bbcr register is configured as follows: bit name reset description 15-9 reserved 0 reserved. 8-0 brxbl(8:0) 0 backplane receive ber length bits the binary value of these bits define the number of channels in addition to the start channel allocated for the ber receiver. (i.e. total channels = start channel + brxbl value) table 38 - backplane receive ber length (brxblr) bits bit name reset description 15-14 reserved 0 reserved. 13-9 bbrsa(4:0) 0 backplane ber receive stream address bits the binary value of these bits defines the backplane input stream that receives the ber data. 8-0 bbrca(8:0) 0 backplane ber receive channel address bits the binary value of these bits defi ne the backplane input start channel in which the ber data will be received. table 39 - backplane ber start receive register (bbsrr) bits bit name reset description 15-0 bbc(15:0) 0 backplane bit error rate count the binary value of these bits def ine the backplane bit error count. table 40 - backplane ber count register (bbcr) bits MT90870 data sheet 67 zarlink semiconductor inc. 13.12 local bit rate registers 13.12.1 local input bit rate registers (librr0-15) address 00cdh to 00dch. sixteen local input bit rate registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16 mb/s. the librr registers are conf igured as follows: 13.12.2 local output bit rate resisters (lobrr0-15) address 00edh to 00fch. sixteen local output bit rate registers allow the bit rate fo r each individual stream to be set to 2, 4, 8 or 16 mb/s. the lobrr registers are configured as follows: librn (for n=0 to 15) name reset description 15-2 reserved 0 reserved 1-0 libr(1:0) 0 local input bit rate table 41 - local input bit rate register (librrn) bits libr1 libr0 bit rate for stream n 00 2mb/s 01 4mb/s 10 8mb/s 11 16mb/s table 42 - local input bit rate (libr) programming table lobrn bit (where n = 0 to 15) name reset description 15-2 reserved 0 reserved 1-0 lobr(1:0) 0 local output bit rate table 43 - local output bit rate register (lobrrn) bits lobr1 lobr0 bit rate for stream n 00 2mb/s 01 4mb/s 10 8mb/s 11 16mb/s table 44 - output bit rate (lobr) programming register MT90870 data sheet 68 zarlink semiconductor inc. 13.13 backplane bit rate registers 13.13.1 backplane input bit rate registers (bibrr0-31) address 010dh to 012ch thirty-two backplane input bit rate registers allow the bit ra te for each individual stream to be set to 2, 4, 8 or 16 mb/s. these registers may be overridden by setting 32 mb/s mode in the control register, in which case, backplane streams 0-15 will operate at 32 mb/s and ba ckplane streams 16-31 will be unused. the bibrr registers are configured as follows: 13.13.2 backplane output bit rate registers (bobrr0-31) address 012dh to 014ch thirty-two backplane output bit rate registers allow the bit ra te for each individual stream to be set to 2, 4, 8 or 16 mb/s.these registers may be overridden by setting 32 mb/s mode in the control register, in which case, backplane streams 0-15 will operate at 32 mb/s and backplane streams 16- 31 will be unused. the bobrr registers are configured as follows: bibrn bit ( for n=0 to 31) name reset description 15-2 reserved 0 reserved 1-0 bibr(1:0) 0 backplane input bit rate table 45 - backplane input bit rate register (bibrrn) bits bibr1 bibr0 bit rate for stream n 00 2mb/s 01 4mb/s 10 8mb/s 11 16mb/s table 46 - backplane input bit rate (bibr) programming table bobrn bit (for n=0 to 31) name reset description 15-2 reserved 0 reserved 1-0 bobr(1:0) 0 backplane output bit rate table 47 - backplane output bit rate register (bobrrn) bits MT90870 data sheet 69 zarlink semiconductor inc. 13.14 memory bist register address 014dh the memory bist register enables the built-in-self-test function for the on-chip memory testing. two consecutive write operations are required to start mbist. the first with only bit 12 (lv_tm) set high (i.e. 1000h), the second with bit 12 maintained high but with the required start bit(s) set high. the mbistr register is configured as follows: bobr1 bobr0 bit rate for stream n 00 2mb/s 01 4mb/s 1 0 8mb/s 1 1 16mb/s table 48 - backplane output bit rate (bobrr) programming table bit name reset description 15-13 reserved 0 reserved. 12 lv_tm 0 mbist test enable. high for mbist mode, low for scan mode. 11 bistsdb 0 backplane data memory start bist sequence. sequence enabled on low to high transition. 10 bistcdb 0 backplane data memory bist sequence completed. (read only). high indicates completion of memory bist sequence. 9bistpdb 0 backplane data memory pass/fail bit (read only). this bit indicates the pass/fail status following completion of the memory bist sequence. a high indicates pass, a low indicates fail. 8bistsdl 0 local data memory start bist sequence. sequence enabled on low to high transition. 7 bistcdl 0 local data memory bist sequence completed. (read only). high indicates completion of memory bist sequence. 6bistpdl 0 local data memory pass/fail bit (read only). this bit indicates the pass/fail status following completion of the memory bist sequence. a high indicates pass, a low indicates fail. 5bistscb 0 backplane connection memory start bist sequence. sequence enabled on low to high transition. 4 bistccb 0 backplane connection memory bist sequence completed. (read only). high indicates completion of memory bist sequence. table 49 - memory bist register (mbistr) bits MT90870 data sheet 70 zarlink semiconductor inc. 13.15 revision control register address 3fffh the revision control register stores the binary value of the silicon revisi on number. this register is read only. the rcr register is configured as follows: 3bistpcb 0 backplane connection memory pass/fail bit (read only). this bit indicates the pass/fail status following completion of the memory bist sequence. a high indicates pass, a low indicates fail. 2bistscl 0 local connection memory start bist sequence. sequence enabled on low to high transition. 1 bistccl 0 local connection memory bist sequence completed. (read only). high indicates completion of memory bist sequence. 0bistpcl 0 local connection memory pass/fail bit (read only). this bit indicates the pass/fail status following completion of the memory bist sequence. a high indicates pass, a low indicates fail. bit name reset value description 15-4 reserved 0 reserved. 3-0 rc(3:0) defined by silicon revision control bits. table 50 - revision control register (rcr) bits bit name reset description table 49 - memory bist register (mbistr) bits (continued) MT90870 data sheet 71 zarlink semiconductor inc. dc electrical characteristics * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. voltages are with respect to ground (v ss ) unless otherwise stated. absolute maximum ratings* parameter symbol min. max. units 1 core supply voltage v dd_core -0.5 2.5 v 2 i/o supply voltage v dd_io -0.5 5.0 v 3 pll supply voltage v dd_pll -0.5 2.5 v 4 input voltage (non-5v tolerant inputs) v i -0.5 v dd_io +0.5 v 5 input voltage (5v tolerant inputs) v i_5v -0.5 7.0 v 6 continuous current at digital outputs i o 15 ma 7 package power dissipation p d 2w 8 storage temperature t s - 55 +125 c recommended operating conditions characteristics sym. min. typ. max. units 1 operating temperature t op -40 25 +85 c 2 positive supply v dd_io 3.0 3.3 3.6 v 3 positive supply v dd_core 1.62 1.8 1.98 v 4 positive supply v dd_pll 1.62 1.8 1.98 v 5 input voltage v i 03.3v dd_io v 6 input voltage on 5 v tolerant inputs v i_5v 055.5v MT90870 data sheet 72 zarlink semiconductor inc. voltages are with respect to ground (v ss ) unless otherwise stated. dc electrical parameters characteristics sym. min. typ . max. units test conditions 1a 1b i n p u t s supply current i dd _ core 4mastatic i dd_core and pll current supply current i dd_core 160 200 ma applied clock c8i = 8.192 mhz 1c supply current i dd_io 100 astatic i dd_io 1d supply current i dd_io 85 ma i av with all output streams at max. data-rate 2 input high voltage v ih 2.0 v 3 input low voltage v il 0.8 v 4 input leakage (input pins) input leakage (bi- directional pins) i il i bl 5 5 a a 0 < v i < v dd_io weak pullup current i pu -200 a input at 0v 5 weak pulldown current i pd 200 a input at v dd_io 6 input pin capacitance c i 5pf 7o u t p u t s output high voltage v oh 2.4 v i oh = 10ma 8 output low voltage v ol 0.4 v i ol = 10ma 9 high impedance leakage i oz 5 a0 < v o < v dd_io 10 output pin capacitance c o 5pf ac electrical characteristics timing parameter measurement: voltage levels characteristics sym. level units conditions 1 cmos threshold v ct 0.5v dd_io v3.0v < v dd_io < 3.6v 2 rise/fall threshold voltage high v hm 0.7v dd_io v3.0v < v dd_io < 3.6v 3 rise/fall threshold voltage low v lm 0.3v dd_io v3.0v < v dd_io < 3.6v MT90870 data sheet 73 zarlink semiconductor inc. backplane and local clock timing characteristic sym. min. typ. max. units notes 1 backplane frame pulse width t bfpw244 t bfpw122 t bgfpw 210 10 10 244 122 122 350 220 220 ns 2 backplane frame pulse setup time before c8i clock rising edge t bfps244 t bfps122 t bgfps 5 5 5 110 110 110 ns 3 backplane frame pulse hold time from c8i clock rising edge t bfph244 t bfph122 t bgfph 5 5 5 110 110 110 ns 4 c8i clock period t bcp8 120 122 124 ns 5 c8i clock pulse width high t bch8 50 61 70 ns 6 c8i clock pulse width low t bcl8 50 61 70 ns 7 c8i clock rise/fall time t rbc8i , t fbc8i 02 3ns 8 c8i cycle to cycle variation t cvc8i 3ns 9 local frame boundary offset t lfbos 7.5 ns 10 fp8o width t lfpw8 t gfpw8 117 117 122 122 127 127 ns c l =60pf 11 fp8o output delay from edge to local frame boundary t fodf8 t gfps8 o 56 56 68 56 ns 12 fp8o output delay from local frame boundary to edge t fodr8 t gfph8 o 59 59 61 61 ns 13 c8o clock period t lcp8 117 127 ns c l =60pf 14 c8o clock pulse width high t lch8 56 68 ns 15 c8o clock pulse width low t lcl8 59 61 ns 16 c8o clock rise/fall time t rlc8o , t flc8o 37ns 17 fp16o width t fpw16 62 66 ns c l =60pf 18 fp16o output delay from falling edge to local frame boundary t fodf16 -29 -36 ns 19 fp16o output delay from local frame boundary to rising edge t fodr16 30 33 ns MT90870 data sheet 74 zarlink semiconductor inc. 20 c16o clock period t lcp16 62 66 ns c l =60pf 21 c16o clock pulse width high t lch16 29 36 ns 22 c16o clock pulse width low t lcl16 30 33 ns 23 c16o clock rise/fall time t rlc16o , t flc16o 05ns backplane and local clock timing (continued) characteristic sym. min. typ. max. units notes MT90870 data sheet 75 zarlink semiconductor inc. figure 20 - backplane and local clock timing diagram for st-bus t lfodr8 t lfodf8 t fodr16 t fodf16 t lch8 t lcl8 t lcl16 t lch16 t lcp8 t lcp16 t flc8o t rlc8o t rlc16o t flc16o * ck_int is the internal clock signal of 131.072 mhz fp8o c8o fp16o c16o t lfpw8_244 t fodr8_244 t fodf8_244 fp8o (244ns) (122 ns) t lfpw8 t fpw16 t bfpw122 t bfph122 t bfps122 ck_int * t lfbos fp8i c8i t bcl8 t bch8 t bcp8 t rbc8i t fbc8i t bfpw244 t bfph244 t bfps244 fp8i (244 ns) (122 ns) MT90870 data sheet 76 zarlink semiconductor inc. figure 21 - backplane and local clock timing for gci-bus t bgfpw t fbc8i t bch8 t bcl8 t rbc8i ck_int* t gfpw8 t gfph8o t gfps8o t frh16o t frs16o t lch8 t lcl8 t lch16 t lcl16 t fpw16 t lcp8 t lcp16 t bcp8 t flc8o t rlc8o t rlc16o t flc16o t lfbos * ck_int is the internal clock signal of 131.072 mhz fp8o c8o fp16o c16o fp8i c8i t bgfph t bgfps MT90870 data sheet 77 zarlink semiconductor inc. backplane data timing characteristic sym. min. typ. max. units notes 1 backplane input data sampling point t bids32 t bids16 t bids8 t bids4 t bids2 18 41 87 178 361 23 46 92 183 366 28 51 97 188 371 ns with zero offset. 2 backplane serial input set-up time t bsis32 t bsis16 t bsis8 t bsis4 t bsis2 2.1 2.1 2.1 2.1 2.1 ns 3 backplane serial input hold time t bsih32 t bsih16 t bsih8 t bsih4 t bsih2 3 3 3 3 3 ns 4 backplane serial output delay t bsod32 t bsod16 t bsod8 t bsod4 t bsod2 10.5 10.5 10.5 10.5 10.5 ns c l =50pf MT90870 data sheet 78 zarlink semiconductor inc. figure 22 - st-bus backplane data timing diagram (8 mb/s, 4 mb/s, 2 mb/s) ck_int * bsti0 - 31 bsto0 - 31 t bids8 8.192 mb/s 8.192 mb/s * ck_int is the internal clock signal of 131.072 mhz fp8i c8i t bids2 t bsih8 t bsis8 t bsih4 t bsis4 t bsih2 t bsis2 t bsod2 t bsod4 t bsod8 bsto0 - 31 4.096 mb/s bsto0 - 31 2.048 mb/s bsti0 - 31 4.096 mb/s bsti0 - 31 2.048 mb/s bit7 ch0 bit6 ch0 bit7 ch0 bit6 ch0 bit0 ch31 bit0 ch63 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit7 ch0 bit6 ch0 bit0 ch31 bit5 ch0 bit4 ch0 bit6 ch0 bit7 ch0 bit0 ch63 bit1 ch127 bit0 ch127 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 6 5 0 4 3 2 1 1 7 t bids4 MT90870 data sheet 79 zarlink semiconductor inc. figure 23 - st-bus backplane data timing diagram (32 mb/s, 16 mb/s) ck_int * fp8i c8i bsti0 - 15 bsto0 - 15 t bids32 32.768 mb/s 32.768 mb/s t bids16 t bsih32 t bsis32 t bsih16 t bsis16 t bsod16 t bsod32 bsto0 - 31 16.384 mb/s bsti0 - 31 16.384 mb/s bit0 ch255 bit7 ch0 bit6 ch0 bit5 ch0 bit7 ch0 bit6 ch0 bit5 ch0 bit6 ch0 bit7 ch0 bit0 bit1 ch511 bit0 ch511 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 6 5 0 4 3 2 1 7 * ck_int is the internal clock signal of 131.072 mhz 2 bit2 ch511 bit1 ch 255 ch 255 MT90870 data sheet 80 zarlink semiconductor inc. figure 24 - gci bus backplane data timing diagram (8 mb/s, 4 mb/s, 2 mb/s) ck_int * bsti0 - 31 bsto0 - 31 tbids8 8.192 mb/s 8.192 mb/s * ck_int is the internal clock signal of 131.072 mhz fp8i c8i tbids4 tbids2 tbsih8 tbsis8 tbsih4 tbsis4 tbsih2 tbsis2 tbsod2 tbsod4 tbsod8 bsto0 - 31 4.096 mb/s bsto0 - 31 2.048 mb/s bsti0 - 31 4.096 mb/s bsti0 - 31 2.048 mb/s bit0 ch0 bit1 ch0 bit0 ch0 bit1 ch0 bit7 ch31 bit7 ch63 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit0 ch0 bit1 ch0 bit7 ch31 bit3 ch0 bit4 ch0 bit2 ch0 bit1 ch0 bit7 ch63 bit6 ch127 bit7 ch127 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 bit6 ch0 1 2 7 3 4 5 6 6 0 MT90870 data sheet 81 zarlink semiconductor inc. figure 25 - gci bus backplane data timing diagram (32 mb/s, 16 mb/s) local clock data timing characteristic sym. min. typ. max. units notes 1 local frame boundary offset t lfbos 7.5 ns 2 input data sampling point t lids16 t lids8 t lids4 t lids2 41 87 178 361 46 92 183 366 51 97 188 371 ns with zero offset. 3 local serial input set-up time t lsis16 t lsis8 t lsis4 t lsis2 2.1 2.1 2.1 2.1 ns 4 local serial input hold time t lsih16 t lsih8 t lsih4 t lsih2 3 3 3 3 ns 5 local serial output delay t lsod16 t lsod8 t lsod4 t lsod2 10.5 10.5 10.5 10.5 ns c l =50pf ck_int * fp8i c8i bsti0 - 15 bsto0 - 15 t bids32 32.768 mb/s 32.768 mb/s t bids16 t bsih32 t bsis32 t bsih16 t bsis16 t bsod16 t bsod32 bsto0 - 31 16.384 mb/s bsti0 - 31 16.384 mb/s bit7 ch255 bit0 ch0 bit1 ch0 bit2 ch0 bit0 ch0 bit1 ch0 bit2 ch0 bit1 ch0 bit0 ch0 bit6 ch 511 bit7 ch 511 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 1 2 7 3 4 5 6 9 * ck_int is the internal clock signal of 131.072 mhz 5 bit5 ch 511 ch255 ch255 bit6 bit7 MT90870 data sheet 82 zarlink semiconductor inc. figure 26 - st-bus local timing diagram (16 mb/s) figure 27 - st-bus local data timing diagram (8 mb/s, 4 mb/s, 2 mb/s) ck_int * fp8i c8i t lids16 t lsih16 t lsis16 t lsod16 lsto0 - 15 16.384 mb/s lsti0 - 15 16.384 mb/s bit0 ch255 bit7 ch0 bit6 ch0 bit5 ch0 bit5 bit6 bit0 * ck_int is the internal clock signal of 131.072mhz bit1 t lfbos ch 255 ch 255 ch 0 ch 0 ch 0 bit7 ck_int * lsti0 - 15 lsto0 - 15 tlids8 8.192 mb/s 8.192 mb/s tlfbos fp8 i c8 i tlids4 tlids2 tlsih8 tlsis8 tlsih4 tlsis4 tlsih2 tlsis2 tlsod2 tlsod4 tlsod8 lsto0 - 15 4.096 mb/s lsto0 - 15 2.048 mb/s lsti0 - 15 4.096 mb/s lsti0 - 15 2.048 mb/s bit7 ch0 bit6 ch0 bit7 ch0 bit6 ch0 bit0 ch31 bit0 ch63 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit7 ch0 bit6 ch0 bit0 ch31 bit5 ch0 bit4 ch0 bit6 ch0 bit7 ch0 bit0 ch63 bit1 ch127 bit0 ch127 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 6 5 0 4 3 2 1 1 7 * ck_int is the internal clock signal of 131.072 mhz MT90870 data sheet 83 zarlink semiconductor inc. note 1: high impedance is measured by pulling to the appropriate rail with r l =1k//1k potential divider, with timing corrected for c l . figure 28 - serial output and external control figure 29 - output driver enable (ode) backplane and local output high-impedance timing characteristic sym. min. typ. max. units test conditions 1 sto delay - active to high-z - high-z to active t dz t zd 4 4 ns ns r l =1k, c l =50pf, see note 1 2 output driver enable (ode) delay to active data output driver enable (ode) delay to high-impedance t ode t odz 15 14 ns ns r l =1k, c l =50pf, see note 1 r l =1k, c l =50pf, see note 1 non-multiplexed microprocessor port timing characteristics sym. min. typ . max. units test conditions 1 cs setup from ds falling t css 0 0ns 2r/w setup from ds falling t rws 8ns 3 address setup from ds falling t ads 8 ns 4cs hold after ds rising t csh 0ns 5r/w hold after ds rising t rwh 8ns tdz sto tzd sto clk vtt vtt hiz valid data vtt hiz valid data vtt hi-z hi-z sto ode todz tode valid data vtt MT90870 data sheet 84 zarlink semiconductor inc. note: 1. high impedance is measured by pulling to the appropriate rail with r l = 1k/1k potential divider, with timing corrected to cancel time taken to charge c l . figure 30 - motorola non-multiplexed bus timing note: there must be a minimum of 30 ns between cpu accesses, to allow the mt90869 device to recognize the accesses as separate (i.e., a minimum of 30 ns must separate the de-assertion of dta (to high) and the assertion of cs and/or ds (to initiate the next access). 6 address hold after ds rising t adh 8 ns 7 data setup from dta low on read t ddr 14 ns c l =60pf 8 data hold on read t dhr 30 ns c l =60pf, r l =1k note 1 9 data setup on write t wds 8ns 10 data hold on write t dhw 8ns 11 acknowledgment delay: reading/writing registers reading/writing memory t akd 85 70 ns ns c l =60pf c l =60pf 12 acknowledgment hold time t akh 12 ns c l =60pf, r l =1k, note 1 non-multiplexed microprocessor port timing characteristics sym. min. typ . max. units test conditions a0-a14 d0-d15 d0-d15 read write t css t csh t adh t dhr t rws t ads t rwh t dhw t akd t wds t ddr t akh v tt v tt v tt v tt v tt v tt v tt valid address valid read data valid write data dta r/w cs ds c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes: www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - 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